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检索条件"任意字段=13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

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Relocation of reconfigurable modules on Xilinx FPGA

Relocation of reconfigurable modules on Xilinx FPGA

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ieee International symposium on design and diagnostics of electronic circuits & systems

作者： Tomas Drahonovsky Martin Rozkovec Ondrej Novak Technical University of Liberec

ISBN: (纸本)9781467361354

this paper presents a design flow that allows relocation of reconfigurable modules on Xilinx FPGAs using dynamic partial reconfiguration (DPR). Relocation of these modules is performed without requirements of re-implementing the design. the article describes the relocation procedure based on modifications of major address of the partial configuration bitstream. this approach allows using single partial bitstream for multiple areas in FPGA device. It reduces a number of partial bitstreams stored in memory, saves the implementation time and it can increase dependability of the system. the proposed flow is demonstrated on a simple example with multiplier and adder locations mutually exchanged.

关键词： FPGA partial reconfiguration Functional block relocation Relocation design flow Field programmable gate arrays configurability bit stream Multiplying circuits

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Improved design of the Uninterruptable Power Supply Unit for Powering of Network Devices

Improved Design of the Uninterruptable Power Supply Unit for...

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ieee International symposium on design and diagnostics of electronic circuits & systems

作者： Martin Pospisilik Petr Neumann Tomas Bata University in Zlin

ISBN: (纸本)9781467361354

Paper describes suggestions on the improvement of the common On-line structure of the uninterruptable power supply units used for powering of network devices. According to these suggestions a prototype circuit able to deliver the output power up to 150 W was constructed. the topology was optimized in order maximum efficiency was achieved when the output is fed by an accumulator in order the operating time was as long as possible.

关键词： Uninterruptable Power Supply Network Devices Power on Ethernet Lead-acid Accumulators power unit Device Network design improvement Output power accumulator operation time line structure topology Suggestion

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Debugging HDL designs Based on Functional Equivalences with High-Level Specifications

Debugging HDL Designs Based on Functional Equivalences with ...

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ieee International symposium on design and diagnostics of electronic circuits & systems

作者： Alexander Finder Jan-Philipp Witte Gorschwin Fey University of Bremen

ISBN: (纸本)9781467361354

the increasing complexity of circuits and systems is forcing design specifications to software-like programming languages like C. Since the conversion from software to hardware is a difficult task solved manually, bugs are frequently introduced in the HDL design. Sophisticated automated error localization and correction techniques, i.e. debugging, are a challenge. In this paper a new automated method is presented for debugging hardware implementations when a software-like specification in C is given. Based on functional equivalences between software and hardware, error localization and correction are automated. We present experimental results for different types of designs and different types of faults.

关键词： Debugging computer software type design Specifications Hardware design languages High-density lipoproteins design specifications Computer hardware Computer Programming Languages functionally equivalent Stuck at faults

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Digital Methods of Offset Compensation in 90nm CMOS Operational Amplifiers

Digital Methods of Offset Compensation in 90nm CMOS Operatio...

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ieee International symposium on design and diagnostics of electronic circuits & systems

作者： Gabriel Nagy Daniel Arbet Viera Stopjakova Slovak University of Technology

ISBN: (纸本)9781467361354

this paper deals with comparison of two discrete methods for digital trimming of the input offset voltage in operation amplifiers designed in 90nm CMOS technology. Two different topologies based on the binary weighed ladder, one using successive approximation register (SAR) and the other employing a simple counter, were compared. Furthermore, a correction circuit was proposed and used to form the mean offset voltage and increase the probability that its value after trimming process will be near zero. Finally, achieved results and improvements are discussed.

关键词： Input offset compensation Operational amplifier 90nm CMOS Digital calibration Analog circuits digital correction analog circuits Operational amplifiers Input Offset Voltage offset compensation trimmings

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Analysis and comparison of functional verification and ATPG for testing design reliability

Analysis and comparison of functional verification and ATPG ...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Marcela Šimková Zdeněk Kotásek Cristiana Bolchini Faculty of Information Technology Brno University of Technology Czech Republic Department Elettronica Informazione e Bioingegneria Politecnico di Milano Italy

As the complexity of current hardware systems rises, it is challenging to harden these systems against faults and to complete their verification and manufacturing test. Not only that verification and testing take a considerable amount of time but the number of design errors, faults and manufacturing defects increases with the rising complexity as well. In this paper we performed a detailed analysis of two approaches devoted to generation of input test vectors with respect to detection of stuck-at faults: the first one is based on classical Automatic Test Pattern Generation, the second one on Constrained-random Stimulus Generation. We evaluated their qualities as well as their drawbacks and introduced ideas about their combination in order to create a new promising approach for testing reliable systems.

关键词： Vectors Circuit faults Automatic test pattern generation Logic gates Reliability Integrated circuit modeling

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Power Analysis Methodology for Secure circuits

Power Analysis Methodology for Secure Circuits

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ieee International symposium on design and diagnostics of electronic circuits & systems

作者： Kamil Gomina Jean-Baptiste Rigaud Philippe Gendrier Philippe Candelier Assia Tria STMicroelectronics Ecole Nationale Superieure des Mines de Saint-Etienne

ISBN: (纸本)9781467361354

A study on power consumption of a digital synchronous circuit in advanced CMOS technology is performed. these technologies target low power applications allowing accurate power analysis. A model of power signature is developed to identify data related consumption using current consumption and power delivery network capacitance at design phase. In addition to digital power characterization tool, device junction capacitance is extracted and used to provide an accurate power signature. Simulations are compared to experimental traces on a synchronous digital circuit to validate the approach. this model can also be used for complex analog/digital circuit. Finally two countermeasures masking and decoupling capacitance flattening is analyzed with our methodology in early design phase allowing to anticipate silicon tests.

关键词： power analysis CMOS technology design phases electricity consumption Power consumption Power (Psychology) Energy sources Silicon capacitance digital synchronization Capacitors Secure Electric circuits LOW POWER digital circuits

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Fault-Tolerant Reconfigurable Low-Power Pseudorandom Number Generator

Fault-Tolerant Reconfigurable Low-Power Pseudorandom Number ...

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ieee International symposium on design and diagnostics of electronic circuits & systems

作者： V. Petrovic Z. Stamenkovic M. Stojcev T. Nikolic G. Jovanovic System Design IHP University of Nis

ISBN: (纸本)9781467361354

the article describes a Fault-Tolerant Reconfigurable Low-power pseudoRandom number Generator (FT_RLRG) which integrates both Fibonacci and Galois LFSRs into a single hardware core. the design of FT_RLRG is of practical interest in testing triple modular fault-tolerant systems in the presence of single event upsets (SEUs), especially in case when the system is SRAM based. the main idea is to design a low-cost and low-power hardware structure which is able to adapt to any standard operating at high-speed with different polynomials (currently up to 32nd order). Proposed FT_RLRG design was implemented as an ASIC in the IHP's 130 nm CMOS technology.

关键词： LFSR Pseudorandom number generator Fault tolerance Reconfiguration Low power Pseudorandom number generator Fault tolerance Linear feedback shift registers LOW POWER Reconfiguration Fibonacci configurability ASIC application specific integrated circuits

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Extensible open-source framework for translating RTL VHDL IP cores to SystemC

Extensible open-source framework for translating RTL VHDL IP...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Saif Abrar Syed Maksim Jenihhin Jaan Raik IBM Bangalore INDIA Tallinn University of Technology Tallinn ESTONIA

SystemC has gained wide acceptance in the design of VLSI SoCs. At the same time there exists a large number of legacy IP cores described in VHDL whose reuse and integration into SystemC ecosystem is highly demanded. However, there is a lack of any standard approach in this regard. this paper proposes an open-source framework and methodology to convert RTL VHDL IP cores to cycle-accurate SystemC designs. the SystemC output is emphasized to be human-readable and providing for clear correspondence to the source VHDL code, thus allowing further manual code changes and debug. the described framework has been implemented based on an open-source zamiaCAD platform and has been successfully applied to translate various VHDL benchmark designs.

关键词： Hardware design languages Open source software Benchmark testing Hardware Sensitivity IP networks Manuals

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On design of Priority-Driven Load-Adaptive Monitoring-Based Hardware for Managing Interrupts in Embedded Event-Triggered Real-Time systems

On Design of Priority-Driven Load-Adaptive Monitoring-Based ...

引用

ieee International symposium on design and diagnostics of electronic circuits & systems

作者： Josef Strnadel Brno University of Technology

ISBN: (纸本)9781467361354

the paper details design of a hardware unit for preventing real-time systems from overloads caused by excessive interrupt rates. Novelty of the hardware can be seen in the fact it is able to adapt interrupt service rate to the RT system load and to the actual priority assignment policy. the load is monitored on basis of special low-overhead signals produced by the system for this purpose. the hardware is designed to pre-process all interrupts before they arrive to the system. then, the hardware is able to buffer each interrupt-related communication until the system is underloaded or running an activity having a lower priority comparing to the interrupt. design of the hardware was described in VHDL and synthesized into Xilinx Spartan-6 devices. Details such as building blocks, overheads and limits related to the realization are presented in this paper.

关键词： Computer hardware interruption precedence real-time systems Overloads very high density lipoproteins Event trigger Building blocks Running

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Fault Collapsing of Multi-Conditional Faults

Fault Collapsing of Multi-Conditional Faults

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ieee International symposium on design and diagnostics of electronic circuits & systems

作者： Rene Krenz-Baath Andreas Glowatz Friedrich Hapke Hochschule Hamm-Lippstadt Mentor Graphics

ISBN: (纸本)9781467361354

Numerous new multi-conditional fault models have been proposed in the last years. In combination with the increasing complexity of today's designs these new fault models cause a tremendous increase of the ATPG-runtime. In this paper we present a novel fault collapsing scheme for multi-conditional faults. the objective is to significantly reduce the fault set and hence reduce runtime for ATPG and fault diagnosis. the collapsing technique consists of three individual collapsing stages, which are individually discussed and evaluated. Additionally we provide an extensive set of experimental results including runtimes of a state-of-the-art ATPG-tool applied on a set of large industrial designs. We will demonstrate that the achieved reduction of up to 48% of the number of faults also reduces the ATPG runtime significantly.

关键词： Fault Collapsing Runtime fault set faults automatic test pattern generation Fault diagnosis Product design

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