检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

665 篇 会议
18 篇 期刊文献

馆藏范围

683 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

472 篇 工学
- 398 篇 电气工程
- 185 篇 电子科学与技术（可...
- 151 篇 计算机科学与技术...
- 24 篇 材料科学与工程（可...
- 16 篇 软件工程
- 8 篇 机械工程
- 7 篇 信息与通信工程
- 7 篇 控制科学与工程
- 4 篇 交通运输工程
- 3 篇 安全科学与工程
- 2 篇 动力工程及工程热...
- 2 篇 建筑学
- 2 篇 土木工程
- 2 篇 化学工程与技术
- 2 篇 网络空间安全
- 1 篇 力学（可授工学、理...
- 1 篇 仪器科学与技术
- 1 篇 林业工程
13 篇 理学
- 7 篇 数学
- 5 篇 物理学
- 3 篇 系统科学
- 1 篇 统计学（可授理学、...
6 篇 管理学
- 5 篇 管理科学与工程(可...
- 1 篇 图书情报与档案管...

主题

36 篇 hardware
31 篇 field programmab...
30 篇 circuit faults
29 篇 cmos integrated ...
22 篇 logic gates
21 篇 integrated circu...
21 篇 clocks
20 篇 digital circuits
19 篇 reliability
19 篇 circuit testing
19 篇 algorithm design...
19 篇 delay
19 篇 cmos technology
17 篇 power demand
17 篇 electronic circu...
16 篇 timing circuits
15 篇 analog circuits
15 篇 fpga
14 篇 hardware design ...
14 篇 optimization

机构

12 篇 faculty of infor...
8 篇 univ bremen inst...
8 篇 brno univ techno...
7 篇 slovak univ tech...
6 篇 ihp technol pk 2...
5 篇 institute of com...
5 篇 univ oslo dept i...
5 篇 warsaw univ tech...
4 篇 ihp im technolog...
4 篇 univ tokyo vlsi ...
4 篇 univ manchester ...
4 篇 dfki gmbh cyber ...
4 篇 brno univ techno...
4 篇 silesian tech un...
4 篇 infineon technol...
4 篇 st microelect gr...
4 篇 norwegian univer...
4 篇 warsaw univ tech...
4 篇 ihp
3 篇 johannes kepler ...

作者

12 篇 sekanina lukas
11 篇 stopjakova viera
11 篇 pleskacz witold ...
10 篇 drechsler rolf
10 篇 asada kunihiro
8 篇 rolf drechsler
8 篇 steininger andre...
8 篇 kerkhoff hans g.
7 篇 kubatova hana
7 篇 krstic milos
7 篇 raik jaan
7 篇 ubar raimund
7 篇 bosio alberto
7 篇 vierhaus heinric...
7 篇 borejko tomasz
6 篇 arbet daniel
6 篇 siwiec krzysztof
6 篇 viera stopjakova
6 篇 nakura toru
6 篇 klaus hofmann

语言

682 篇 英文
1 篇 中文

检索条件"任意字段=13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

共 683 条记录，以下是341-350 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Cross-layer resilient system design

Cross-layer resilient system design

引用

ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Mehdi Tahoori Karlsruhe Institute of Technology Karlsruhe Germany

Summary form only given. Improvements in chip manufacturing technology have propelled an astonishing growth of computing systems which are integrated into our daily lives. However, this trend is facing serious challenges, both at device and system levels. At the device level, as the minimum feature size continues to shrink, a host of vulnerabilities influence the robustness, reliability, and availability of embedded and critical systems. Some of these factors are caused by the stochastic nature of the nanoscale manufacturing process (e.g., process variability, sub-wavelength lithographic inaccuracies), while other factors appear because of high frequencies and nanoscale features (e.g. RLC noise, on-chip temperature variation, increased sensitivity to radiation and transistor aging). At the other end of the spectrum, these systems are seeing a tremendous increase in software content. Whereas traditional software design paradigms have assumed that the underlying hardware is fully predictable and error-free, there is now a critical need to build a software stack that is responsive to variations, and resilient against emerging vulnerabilities in the underlying hardware. To cost-efficiently tackle resiliency challenges, a new “cross-layer” trend has emerged in which different levels of design stacks, in hardware and software, work together to find a globally optimal solution. the interdisciplinary topic of cross layer resiliency cross various disciplines and requires collaboration and cooperation of various communities such as design automation, testing and design for testability, computer architecture, embedded systems and software, validation and verification, fabrication, device, circuits, and systems. Such cross-layer approach will lead to possible paradigm shifts to consider reliability throughout the design flow, from devices to systems and applications.

关键词： Tutorials

来源：评论

学校读者我要写书评

暂无评论

A New Method for Correcting Time and Soft Errors in Combinational circuits

A New Method for Correcting Time and Soft Errors in Combinat...

引用

ieee International symposium on design and diagnostics of electronic circuits & systems

作者： Egor S. Sogomonyan Stefan Weidling Michael Goessel University of Potsdam

ISBN: (纸本)9781467361354

In this paper a simple method for fault tolerance with respect to transient or soft errors in the combinational part of sequential circuits is investigated. the memory elements of the sequential circuits are fault-tolerant master-slave-flip-flops. For correcting errors in the combinational part instead of error-correcting codes (ECCs) much simpler error-detecting codes can be used. An error detection signal indicating an error in a combinational part of the circuit blocks the clock signal in the second half of the clock cycle with the result that the previous correct state values of all the slave latches are preserved as long as the transient error (of any duration) stays in the combinational circuit. As soon as the transient error disappears, the system can continue to work from a correct state immediately;no complicated restart of the system is necessary. the system has only to stop for the duration of the transient error. the necessary time delay of the error signal determined by the error-detecting code limits the length of the clock cycle for which the proposed method is applicable. therefore simple error-detecting codes such as parity codes, split-parity codes and duplication codes should be used. For the mentioned codes the time delay and the error detection probabilities which correspond to the error correction probabilities of this method are determined for benchmark circuits experimentally.

关键词： Combinational circuits transient errors clock cycle error detection codes Fault tolerance sequential circuits clock signal Codes time delay error correction Error detection

来源：评论

学校读者我要写书评

暂无评论

An Area Efficient Hardware Architecture design for H.264/AVC Intra Prediction Reconstruction Path based on Partial Reconfiguration

An Area Efficient Hardware Architecture Design for H.264/AVC...

引用

ieee International symposium on design and diagnostics of electronic circuits & systems

作者： Milica Orlandic Kjetil Svarstad Norwegian University of Science and Technology

ISBN: (纸本)9781467361354

the H.264/AVC standard supports intra prediction in order to reduce spatial redundancy in the video frame. the intra prediction process for one macro block requires reconstructing the left and top neighbor macro blocks where the reconstruction path includes a number of processing units such as integer transform, quantization, inverse quantization and inverse integer transform. In order to meet the real time performance constraints of different video standards, a high throughput through this path is necessary. In this paper we propose architecture for real time implementation of the reconstruction path used in the H.264/AVC where the hardware is designed to be used as part of a complete H.264 video coding system. Each processing block executes in a single clock cycle for all calculations required for one 4×4 block. In order to minimize area cost while maintaining the performance, dynamic partial reconfiguration is employed in the quantization and inverse quantization modules such that an area - efficient solution is found without impairing the throughput.

关键词： Integer DCT H.264 Quantization FPGA implementation Inverse quantization Inverse integer DCT Partial reconfiguration Quantization macro block clock cycle video standards spatial redundancy Reconfiguration Reconstructive Surgical Procedures hardware architecture

来源：评论

学校读者我要写书评

暂无评论

External Capacitorless Low Dropout Linear Regulator Using Cascode Structure

External Capacitorless Low Dropout Linear Regulator Using Ca...

引用

ieee International symposium on design and diagnostics of electronic circuits & systems

作者： Hong-Yi Huang Cheng-Yu Chen Kuo-Hsing Cheng National Taipei University National Central University

ISBN: (纸本)9781467361354

Recent developments in system-on-chip (SoC) applications lead to an increasing attention on biomedical implantable IC designs. Being implantable, a CMOS low dropout regulator (LDR) with high power supply rejection (PSR) must have an on-chip output capacitor. To achieve a high PSR over a wide frequency range, a cascode technique with power NMOS and power PMOS is utilized to increase the output impedance of the LDR so that the output voltage can be less susceptible to any changes in the input voltage. With this technique, a clean and stable voltage can be produced. the test chip is implemented by TSMC 0.18μm 1P6M CMOS technology with an area of 0.872×0.561 mm~2. the measured PSR at full load without using large external output capacitor is -33.6 dB at 60MHz and the ripple is 28mV. the power consumption is 2.13 mW and the efficiency is 77%.

关键词： Current feedback compensation Capacitor-free LDO Power supply rejection (PSR) output capacitor Output impedance test chip Input Voltage LAND DISPOSAL RESTRICTIONS cascode output voltage PRIMARY SYSTEM RELIEF linear quadratic regulators full load ripples integrated circuit design Power consumption system-on-chip Implants and Prostheses

来源：评论

学校读者我要写书评

暂无评论

Hardware-Software Co-Visualization: Developing systems in the Holodeck

Hardware-Software Co-Visualization: Developing Systems in th...

引用

ieee International symposium on design and diagnostics of electronic circuits & systems

作者： Rolf Drechsler Mathias Soeken University of Bremen

ISBN: (纸本)9781467361354

Modern systems consisting of hardware and software are becoming more and more complex. the underlying data of next generation systems will consist of billions of entries in terms of components or lines of code. Handling this data efficiently is one of the major challenges for future EDA. In order to provide a meaningful preparation for these complex issues it is inevitable to deal with highly elaborated visualization techniques. It is unimaginable how data sets of this size could be grasped without advanced plotting methods. Although a lot of effort has been put into research for visualization of hardware and software, techniques hardly exist that consider them in combination. Besides that, in most cases visualization techniques concentrate on the illustration of the system's structure and behavior, e.g. to ease debugging. However, far more information can be integrated. As an example, in the context of verification the accentuation of coverage metrics on top of the structural visualization of a system would immediately pinpoint the verification engineer to areas that are poorly validated. Furthermore, when considering the co-design of hardware-software systems, design exploration can be carried out much easier when the designer gets immediate visual feedback. Inspired by recent achievements in visualization methods and the invention of sophisticated machinery, in this invited paper we propose the use of Hardware-Software Co-Visualization (HSCV). the potential of current techniques as well as their limitations will be demonstrated. Furthermore, we are seeking for alternative methods in system visualization that go beyond monitors and printed pages. Techniques from 3D rendering and virtual reality are utilized for this purpose leading to a holistic environment in which complex systems can be grasped within seconds just as huge data sets in the context of plots. State-of-the-art is presented and directions for future work are outlined.

关键词： Visualization Computer hardware visualization methods lines of code Co-design ELECTRIC POWER GENERATION systems Inventions MONITOR alternative methods computer software Complex systems virtual reality ILLUSTRATIONS entry

来源：评论

学校读者我要写书评

暂无评论

Area-Speed efficient modular architecture for GF{2~m) multipliers dedicated for cryptographic applications

Area-Speed efficient modular architecture for GF{2~m) multip...

引用

ieee International symposium on design and diagnostics of electronic circuits & systems

作者： Danuta Pamula Edward Hrynkiewicz Silesian University of Technology

ISBN: (纸本)9781467361354

Arithmetic operations over GF(2~m) have wide applications in many domains, especially in cryptography. Cryptographic applications of GF(2~m) arithmetic units are the most demanding applications. the binary finite field extension multipliers are components of elliptic curve cryptography (ECC) systems and perform crucial operations in the system. In fact all operations in the system are sequences of operations in the finite field. thus, the efficiency, in terms of speed and area of the finite-field units, significantly impacts efficiency of ECC systems. In this paper we propose a modified approach to construction of area-speed efficient modular GF(2~m) multiplier operating on fields of large sizes defined in cryptographic standards (thus on large numbers c. 160-600 bits), which leads to increase of the overall area-speed efficiency of the architecture. To increase the efficiency of the multiplier we have combined bit-parallel and bit-serial manner of processing input operands. the proposed architecture is modular;it does not require redesign of the multiplier if we decide to change the field size used. We present two architectures, dedicated to FPGA circuit, of modular block which constitutes the proposed GF(2~m) multiplier. the article details variations of the multiplier architecture, which impact its speed or area and shows how its parameters scale for different field sizes.

关键词： Multiplying circuits Modularity ARCHITECTURE field size Elliptic curve cryptography Building construction Surgery Galois fields Redesign

来源：评论

学校读者我要写书评

暂无评论

the design of Dependable Flexible Multi-Sensory System-on-Chips for Security Applications

The Design of Dependable Flexible Multi-Sensory System-on-Ch...

引用

ieee 15th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Kerkhoff, Hans G. Zhao, Yong Univ Twente Ctr Telemat & Informat Technol CTIT Testable Design & Test Integrated Syst TDT Grp NL-7500 AE Enschede Netherlands

ISBN: (纸本)9781467311854

a new approach towards highly reconfigurable SoCs for data-streaming multi-sensory systems is presented. As the applications are in the security arena, a very high degree of dependability should be guaranteed. For this purpose, extensive use is made of many-core processor architectures and associated embedded health-monitoring circuits. this enables the preventive (automatic) repair by spare parts or priority ranking of tasks among processors.

关键词： flexible multi-sensory systems nanoelectronics dependability embedded health monitoring security

来源：评论

学校读者我要写书评

暂无评论

Automated Debugging from Pre-Silicon to Post-Silicon

Automated Debugging from Pre-Silicon to Post-Silicon

引用

ieee 15th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Dehbashi, Mehdi Fey, Goerschwin Univ Bremen Inst Comp Sci D-28359 Bremen Germany

ISBN: (纸本)9781467311854

Due to the increasing design size and complexity of modern Integrated circuits (IC) and the decreasing time-to-market, debugging is one of the major bottlenecks in the IC development cycle. this paper presents a generalized approach to automate debugging which can be used in different scenarios from design debugging to post-silicon debugging. the approach is based on model-based diagnosis. Diagnostic traces are proposed as an enhancement reducing debugging time and increasing diagnosis accuracy. the experimental results show the effectiveness of the approach in post-silicon debugging.

关键词： Debugging diagnosis quality/standard Integrated circuits Automation

来源：评论

学校读者我要写书评

暂无评论

Bounded Model Checking of Contiki Applications

Bounded Model Checking of Contiki Applications

引用

ieee 15th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Voertler, thilo Ruelke, Steffen Hofstedt, Petra Fraunhofer Inst Integrated Circuits IIS Design Automat Div EAS Zeunerstr 38 D-01069 Dresden Germany Brandenburg Tech Univ Cottbus Dept Comp Sci D-03013 Cottbus Germany

ISBN: (纸本)9781467311854

Verification of embedded systems is a challenge due to the tight combination of hardware and software. We present an approach on the automatic verification of embedded system applications for the operating system Contiki using a standard bounded model checking tool for software. By using an operating system a higher abstraction level to hardware is possible. Our approach is therefore easily applicable for the verification of different hardware platforms.

关键词： Model checking Embedded systems Hardware Platform Verification computer software Computer hardware Operating systems Bounded

来源：评论

学校读者我要写书评

暂无评论

Generation of Non-Overlapping Clock Signals without using a Feedback Loop

Generation of Non-Overlapping Clock Signals without using a ...

引用

ieee 15th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Spilka, R. Hilber, G. Rauchenecker, A. Gruber, D. Sams, M. Ostermann, T. Johannes Kepler Univ Linz Inst Integrated Circuits A-4040 Linz Austria

ISBN: (纸本)9781467311854

Within the field of delta-sigma modulators utilizing switched-capacitor structures it is of great importance to use non-overlapping clocks. the circuit presented in this document generates these signals without the need of feedback loops. To verify the timing of non-overlapping clocks, an integrated circuit is introduced that is capable of sampling fast clock signals and forwards the processed data to the measurement equipment.

关键词： delta sigma modulator non-overlapping clock feedback sampling on-chip sampling

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共69页 << < 31 32 33 34 35 36 37 38 39 40 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：