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检索条件"任意字段=13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

共 683 条记录，以下是361-370 订阅

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VARMA-VARiability Modelling and Analysis Tool

VARMA-VARiability Modelling and Analysis Tool

引用

ieee 15th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Russell, G. Burns, F. Yakovlev, A. Newcastle Univ Sch Elect Elect & Comp Engn Newcastle Upon Tyne NE1 7RU Tyne & Wear England

ISBN: (纸本)9781467311854

Process parameter variability in IC manufacturing has become an increasingly important issue as feature scaling descends further into the deep submicron region. Within industry the development of EDA tools associated with 'process-aware-design' has a high priority as the impact on circuit performance due to process variations is having increasingly adverse effects on yield and performance. VARMA is a variability analysis tool which enables optimisation of both manufacturing process and nano-electronic circuit design in order to avoid 'manufacturing surprises' resulting in costly chip respins, delays in reaching the market place and the subsequent loss of profitability.

关键词： VLSI design process variability CAD tools

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Online Fault diagnostics and Impedance Signature Mapping of High Temperature PEM Fuel Cells Using Rapid Small Signal Injection

Online Fault Diagnostics and Impedance Signature Mapping of ...

引用

Annual Conference of the ieee Industrial electronics Society

作者： Chris de Beer Paul Barendse Pragasen Pillay Brian Bullecks Raghunathan Rengaswamy Department of Electrical Engineering University of Cape Town Department of Chemical Engineering Texas Tech University

ISBN: (纸本)9781479902255

the recent development of electric vehicles and electronic equipment has resulted in a demand for portable power supply systems with high power density and life expectancy. High Temperature (HT) Proton Exchange Membrane (PEM) fuel cells have emerged as a possible solution to this requirement. Recent advances in the materials allow the cells to operate at higher temperatures resulting in a number of advantages. these systems still suffer from degradation mechanisms that can degrade performance and decrease the life expectancy. In order to diagnose the fuel cell performance and degradation mechanisms, impedance analysis can be performed. this paper presents a design for the power electronic hardware that can perform these analyses online for single cell applications, where the output voltage is very low. Special consideration must be given to the hardware selection and small signal injection capability. the Nyquist plots and small amplitude current step voltage response of the HTPEM fuel cell is presented along with those captured after catalyst degradation has occurred. It is shown how the online system can capture these changes by using equivalent circuits.

关键词： HTPEM Nyquist plots Electrochemical impedance Voltage collapse Degradation Nyquist diagrams Voltage collapse signal injection fuel batteries life expectancy Online systems Polymer electrolyte membrane fuel cells deterioration Fault diagnosis output voltage

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Complementary Edge Alignment and Digital Output Signal Speed-Up CMOS Positive Feedback Latches

Complementary Edge Alignment and Digital Output Signal Speed...

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ieee 15th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Milovanovic, Vladimir Zimmermann, Horst Vienna Univ Technol TU Wien Inst Electrodynam Microwave & Circuit Engn EMCE A-1040 Vienna Austria

ISBN: (纸本)9781467311854

the paper elaborates on a kind of positive feedback latch that is not used as a memory element but rather for purposes of complementary signal edge alignment and digital output signal speed-up. the theoretical background behind positive exponential rise latches is presented in detail. the proposed latch is fully differential, fully complementary and perfectly symmetrical. It is structurally composed through comparisons with the set-reset (SR) latch and is implemented in CMOS technology. Simulation results show that the proposed circuit improves the state switching ability thus relaxing the design constraints connected to the latch interface. the latch, hence allows larger optimization space which leads to a better design.

关键词： Latch Device Component memory element design constraints outgoing signal Speeding Complementary

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A low-overhead Monitoring Ring Interconnect for MPSoC Parameter Optimization

A low-overhead Monitoring Ring Interconnect for MPSoC Parame...

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ieee 15th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Bouajila, Abdelmajid Lakhtel, Abdallah Zeppenfeld, Johannes Stechele, Walter Herkersdorf, Andreas Tech Univ Munich Inst Integrated Syst D-80290 Munich Germany

ISBN: (纸本)9781467311854

MPSoCs need to integrate self-x properties in order to get rid of the worst-case design style which is no longer affordable in large SoCs. Integrating self-x properties in SoCs is possible through a monitoring interconnect which carries monitor information to evaluators that decide on actions that will tune the SoC operation mode. We have designed a customized interconnect for SoC monitoring/actuation. We have implemented it in VHDL and tested it in FPGA. the prototype proved that this customized interconnect provides good results regarding latency and area overheads and is a key component in enabling self-optimization in our FPGA MPSoC prototype.

关键词： SYNthETIC ORGANIC CHEMICALS Evaluators Parameter optimization Enabling Crucial components worst case design Latency adaptive optimization RID

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Digital-Driven Formal Analog Verification for Asynchronously Feed-Backed Circuitries

Digital-Driven Formal Analog Verification for Asynchronously...

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ieee 15th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Uygur, Guerkan Sattler, Sebastian M. Univ Erlangen Nurnberg LZS Chair Reliable Circuits & Syst D-91052 Erlangen Germany

ISBN: (纸本)9781467311854

In this paper we show a road map for successively dividing an asynchronously feed-backed circuitry into its substructures, and provide several intuitive and formal approaches to recompose structural behavior from its substructures. Each dividing granularity and composition provides specific information about safety, stability, reliability and reproducibility. We further classify and discuss behavioral model and stability criteria on bases of the given structural properties and present a use-case. Implementation results are given and discussed formally with respect to extracted structure-weaknesses and safety aspects. the method exhibits analog properties of the structure like multivalued information flow, propagation time and superpositions that can lead to information corruptness.

关键词： analog formal verification asynchronous feed-back structural decomposition composition safety-critical stability reliability reproducibility

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LC-VCO design Automation Tool for Nanometer CMOS Technology

LC-VCO Design Automation Tool for Nanometer CMOS Technology

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ieee 15th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Siwiec, Krzysztof Borejko, Tomasz Pleskacz, Witold A. Warsaw Univ Technol Inst Microelect & Optoelect PL-00662 Warsaw Poland

ISBN: (纸本)9781467311854

In this paper a low-voltage LC voltage-controlled oscillator (VCO) design automation tool has been presented. the tool is based on design methodology, which takes under consideration trade-offs between power consumption, phase noise and tuning range. NMOS only architecture is considered because of its capability to work with low supply voltages. One of the goals, while creating the tool, was to make it technology independent. this was achieved by creating SKILL scripts that allows fast configuration of design library for specified technology. Trade-offs between power consumption, phase noise and tuning range are analyzed and based on them design flow has been proposed. Finally two design examples in 90 and 130 nm CMOS technology have been presented.

关键词： CMOS technology tuning range Computer-Aided design Phase noise Nanometers Power consumption

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HLS-DoNoC: High-Level Simulator for Dynamically Organizational NoCs

HLS-DoNoC: High-Level Simulator for Dynamically Organization...

引用

ieee 15th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Guang, Liang Nigussie, Ethiopia Plosila, Juha Isoaho, Jouni Tenhunen, Hannu Univ Turku SF-20500 Turku Finland Royal Inst Technol Stockholm Sweden

ISBN: (纸本)9781467311854

A high-level simulator is presented for the design and analysis of dynamically organizational Networks-on-Chip (DoNoCs). the DoNoC is able to organize statically or dynamically different network nodes for run-time coarse and fine grained reconfiguration, in particular power management. As an important step in the design flow, a simulator for early-stage design exploration is the focus of the paper. Built upon classic wormhole-based NoC architecture, the simulator is capable of experimenting diverse run-time monitoring and reconfiguration methods. In particular, dynamic clusterization can be performed with inter-cluster interfaces properly configured at the run-time. the simulator is flit-level accurate, trace-driven, and easy-to-reconfigure. It supports both synchronous and ratiochronous timing, and can provide the communication performance and power/energy consumption. the paper demonstrates the usage of the simulator in the design of various cluster-based power management schemes.

关键词： simulator Runtime design flow Reconfiguration

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D&T Presenter - electronic Interactive System for design and Test Education

D&T Presenter - Electronic Interactive System for Design and...

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ieee 15th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Hlatky, Matej Martinek, Valter Gramatova, Elena Slovak Univ Technol Bratislava Fac Informat & Informat Technol Bratislava Slovakia

ISBN: (纸本)9781467311854

the paper is targeted to current and advanced technologies in education, mainly to electronic interactive education in the design and test fields. Nowadays, many different types of electronic systems exist for e-learning, m-learning, general electronic presentation systems for helping lecturers to make education more attractive and helpful for students. the electronic presentation systems offer teachers to prepare and present their educational materials in simpler way and allow presenting more information, figures and interesting documents for students. Such presentation systems are mainly helpful for teachers but presentation does not have to be attractive for students because they are not actively involved into the education. Current technologies offer Tablet PCs with new input - touch-screen display and stylus for writing some remarks into slides by hand. Both, teachers and students can use this input. But students are not still involved directly into the teaching process, thus a teacher has less information about students' knowledge. In addition, presentation systems are generally implemented in such way the teacher has to prepare all materials before its presentation. the paper presents a new interactive electronic presentation system for design and test of digital circuits. the developed system, named D&T Presenter allows integration of new methods into the education using interactive works with students based on on-line anonymous test and answer sheets during lectures. the presentation system was evaluated at the Slovak University of Technology in Bratislava during the course Testability of digital systems and shows very good and useful feedbacks from students.

关键词： design and test education electronic presentation system

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Efficient Digital design for Automotive Mixed-Signal ASICs Using Simulink

Efficient Digital Design for Automotive Mixed-Signal ASICs U...

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ieee 15th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Mauderer, Andreas Freier, Marvin Oetjens, Jan-Hendrik Rosenstiel, Wolfgang Robert Bosch GmbH Automot Elect Tubinger Str 123 D-72762 Reutlingen Germany Univ Tubingen Dept Comp Engn D-72074 Tubingen Germany

ISBN: (纸本)9781467311854

In common design flows of mixed-signal ASICs, the transition from system-level models to implementation-level models is executed in a manual process that carries potential for an efficiency gain by automation. this contribution addresses this aspect by showing and discussing an approach for efficient automated transitions from digital parts of Simulink models representing heterogeneous systems to VHDL and Verilog descriptions. It describes a design flow, in which a Simulink model representing a digital part of a mixed-signal ASIC is checked and optimized for automated generation of design rule compliant and more efficient digital hardware implementations. For this purpose, modeling guidelines and optimizations were implemented and integrated into an easily usable graphical user interface. thereby, the strategy is based on considering and optimizing the digital part with respect to the surrounding heterogeneous system. An evaluation of the presented design flow is shown by applying the flow to an automotive hardware design.

关键词： design flow automotive engineering computer hardware design HETEROGENEOUS SYSTEM Automation

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design and Implementation of High-Performance High-Valency Ling Adders

Design and Implementation of High-Performance High-Valency L...

引用

ieee 15th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Kocak, Taskin Patil, Preeti Bahcesehir Univ Dept Comp Engn Istanbul Turkey Univ Bristol Dept Elect & Elect Engr Bristol Avon England

ISBN: (纸本)9781467311854

Parallel prefix adders are used for efficient VLSI implementation of binary number additions. Ling architecture offers a faster carry computation stage compared to the conventional parallel prefix adders. Recently, Jackson and Talwar proposed a new method to factorize Ling adders, which helps to reduce the complexity as well as the delay of the adder further. this paper discusses the design and implementation details for such lower complexity, fast parallel prefix adders based on Ling theory of factorization. In particular, valency or radix, the number of inputs to a single node, is explored as a design parameter. Several low and high valency adders are implemented in 65 nm CMOS technology. Experimental results show that the high-valency Ling adders have superior areaxdelay characteristics over previously reported Ling-based or non-Ling adders for the same input size. Moreover, our 20-bit high valency adder has a better areaxdelay measurement than the previously-published 16-bit adders.

关键词： Adders arithmetic integrated circuits logic design

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