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检索条件"任意字段=13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

共 683 条记录，以下是381-390 订阅

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design Techniques for Increasing Performance and Resource Utilization of Reconfigurable Soft CPUs

Design Techniques for Increasing Performance and Resource Ut...

引用

ieee 15th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Wold, Alexander Koch, Dirk Torresen, Jim Univ Oslo Dept Informat N-0316 Oslo Norway

ISBN: (纸本)9781467311854

Reconfigurable hardware allows application specific customization of soft microprocessors. Techniques such as removing unused instructions, software emulation of instructions, custom instruction set extensions, and run-time reconfigurable instructions have been suggested. However, the techniques have largely been studied separately from each other. the contribution of this paper is a classification method enabling integration of these techniques. this allows for generating an application specific microprocessor based system from a given program. the generated microprocessor is optimized with respect to performance per area. the improvement of our methodology is demonstrated for the CoreBench benchmark. the benefit of combining the removal of unused instructions (ISA subsetting) with software emulation of rarely used instructions is shown to increase performance while at the same time reducing resource requirements. Improvement in both area and performance is accomplished thorough simplifying the design allowing an increase in clock frequency for the synthesized soft CPU. Optimizing only by using custom instructions allowed a 12% increase in performance, but also increased resource usage by 6%. Software emulation combined with ISA subsetting allowed area savings of 7%, but only improved performance by 3%. By combining custom instructions, software emulation and ISA subsetting, we achieved an performance improvement of 15% while at the same time reducing resource requirements.

关键词： ISA (Instruction set architecture) subsetting Field Programmable Gate Array (FPGA) Instruction Set Extension (ISE) custom instruction reconfigurable instruction application specific microprocessor

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An Analytical Approach to Efficient Circuit Variability Analysis in Scaled CMOS design

An Analytical Approach to Efficient Circuit Variability Anal...

引用

13th International symposium on Quality electronic design (ISQED)

作者： Gummalla, Samatha Subramaniam, Anupama R. Cao, Yu Chakrabarti, Chaitali Arizona State Univ Sch Elect Comp & Energy Engn Tempe AZ 85287 USA

ISBN: (纸本)9781467310369;9781467310352

CMOS scaling has led to increasingly high variability in device and circuit performance. To improve design robustness, it is important to consider variation in the design flow. In this paper a closed-form solution is proposed to predict the variability in gate timing, which significantly reduces computation cost in statistical analysis. the proposed model covers both nominal delay and its variability across a wide range of device sizes, load capacitances and input transition times. Stack effect, such as that in NAND and NOR gates, is taken into account thereby making the model sensitive to the switching patterns. For ISCAS'85 benchmark circuits, implemented using a 45nm library, the model demonstrates high accuracy with less than 3.5% error for nominal delay and within 5ps variation of the critical path. Finally, use of the proposed model in design flow is demonstrated for setup time violations.

关键词： Timing model variation statistical analysis critical path

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Statistical Observations of NBTI-induced threshold Voltage Shifts on Small Channel-area Devices

Statistical Observations of NBTI-induced Threshold Voltage S...

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13th International symposium on Quality electronic design (ISQED)

作者： Sato, Takashi Awano, Hiromitsu Shimizu, Hirofumi Tsutsui, Hiroshi Ochi, Hiroyuki Kyoto Univ Dept Commun & Comp Engn Sakyo Ku Yoshida Hon Machi Kyoto 6068501 Japan Kyoto Univ Fac Engn Yoshida Hon Machi Kyoto 6068501 Japan

ISBN: (纸本)9781467310369;9781467310352

Performance variability of miniaturized devices has become a major obstacle for designing electronic systems. Temporal degradation of threshold voltages and its variation are going to be an additional concerns to ensure their reliability. In this paper, based on measurement results on large number of devices, we present statistical properties of device degradation and recovery. the measurement data is obtained by using a device-array circuit suitable for efficiently collect statistical data on degradations and recoveries of very small channel-area devices. Stair-like change of threshold voltages found in our measurement suggests that charge trapping and emission may play a key role in the device degradation process.

关键词： threshold voltage Statistical Data CHARGE TRAPPING measurement data electronic systems

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design Quality Tradeoff Studies for 3D ICs Built with Nano-scale TSVs and Devices

Design Quality Tradeoff Studies for 3D ICs Built with Nano-s...

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13th International symposium on Quality electronic design (ISQED)

作者： Yang, Kaiyuan Kim, Dae Hyun Lim, Sung Kyu Tsinghua Univ Inst Microelect Beijing 100084 Peoples R China Georgia Inst Technol Sch Electr & Comp Engn Atlanta GA USA

ISBN: (纸本)9781467310369;9781467310352

three dimensional integrated circuits (3D ICs) built with through-silicon vias (TSVs) have smaller footprint area, shorter wirelength, and better performance than 2D ICs. However, the quality of 3D ICs is strongly dependent on TSV dimensions and parasitics. Using large TSVs may cause silicon area overhead and reduce the amount of wirelength reduction in 3D ICs. In addition, non-negligible TSV parasitic capacitance can result in delay overhead affecting the delay of 3D ICs. Meanwhile, with the development of TSV manufacturing technology, nano-scale TSVs are emerging, which is expected to reduce the overheads caused by using large TSVs. therefore, this paper investigates the impact of nano-scale TSVs on the quality of 3D ICs at future technology nodes. For this study, we develop a 16nm standard cell library, design 3D ICs using different process technologies (45nm, 22nm, and 16nm) and various TSVs diameters (from 5 mu m to 0.1 mu m), and discuss the impact of nano-scale TSVs.

关键词： three dimensional integrated circuits

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Low power balun design for 1.575 GHz in 90 nm CMOS rechnology

Low power balun design for 1.575 GHz in 90 nm CMOS rechnolog...

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2012 ieee 15th International symposium on design and diagnostics of electronic circuits and systems, DDECS 2012

作者： Gradzki, Jacek Institute of Microelectronics and Optoelectronics Warsaw University of Technology ul. Koszykowa 75 00-662 Warszawa Poland EVATRONIX al. Ujazdowskie 18/15 00-478 Warszawa Poland

ISBN: (纸本)9781467311854

In this paper low power balun design is presented. It is optimized for 1.575 GHz and designed in 90 nm UMC CMOS technology. Current consumption is only 0.44 mA under 1.2 V supply voltage. the simulation shows that gain and phase imbalance are equal to 0.08 dB and 0.045°, respectively. Single-ended power gain of this circuit is 2.2 dB. A special dimension matching has been made to minimize circuit susceptibility to variation of the manufacturing process. © 2012 ieee.

关键词： CMOS integrated circuits

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A Case for 3D Stacked Analog circuits in High-Speed Sensing systems

A Case for 3D Stacked Analog Circuits in High-Speed Sensing ...

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13th International symposium on Quality electronic design (ISQED)

作者： Abdel-Majeed, Mohammad Chen, Mike Annavaram, Murali Univ So Calif Dept Elect Engn Los Angeles CA 90089 USA

ISBN: (纸本)9781467310369;9781467310352

In order to build high performance real-time sensing systems every building block in the system should be built with a technology that allows that building block to achieve its best performance. Technologies like BJT and BICMOS are better suited for building basic analog blocks like input buffers and power amplifiers, while CMOS is the best choice for digital data processing. To build mixed-technology systems traditionally system-in-package (SiP) techniques are used. SiP integration uses bonding wires or flip chip instead of on-chip integration. In this paper we study the feasibility of using 3D stacking to integrate heterogeneous blocks built using different technologies within a real-time sensing system. Several of the previous studies on 3D stacking focused on integrating multiple digital blocks and using through-silicon-vias (TSVs) to transfer digital signals between the layers in a stack. In this paper we study the behavior of the analog signals traversing through TSVs and measure how well 3D stacking can enhance or limit the performance of analog and digital stacking. In order to quantify the power and performance characteristics, we modeled bonding wire, flip chip, and through-silicon-via (TSV) interfaces. Using these models we show that 3D stacking of analog and analog/digital components can double the bandwidth, increase sampling frequency by nearly two orders magnitude and and improve the signal integrity by 3 dB compared to bond wires.

关键词： 3D stacking bonding wire interface analog-analog stacking

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A design Tradeoff Study with Monolithic 3D Integration

A Design Tradeoff Study with Monolithic 3D Integration

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13th International symposium on Quality electronic design (ISQED)

作者： Liu, Chang Lim, Sung Kyu Georgia Inst Technol Atlanta GA 30332 USA

ISBN: (纸本)9781467310369;9781467310352

this paper studies various design tradeoffs existing in the monolithic 3D integration technology. Different design styles in monolithic 3D ICs are studied, including transistor-level monolithic integration (MITR) and gate-level integration (MI-G). GDSII-level layout of monolithic 3D designs are constructed and analyzed. Compared with its 2D counterparts, MI-TR designs have advantages in footprint area, wire-length, timing, and power, because of the smaller footprint. MI-G design style also demonstrate advantages in area, timing and power over TSV-based designs, because of the smaller size and parasitics of inter-tier vias compared with TSVs. To further take the advantage of monolithic 3D technology, several technology improvement options are also explored. Besides, some possible design challenges with monolithic 3D are also studied, including global variation and signal integrity issues.

关键词： three dimensional integrated circuits

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Automated Correction of design Errors by Edge Redirection on High-Level Decision Diagrams

Automated Correction of Design Errors by Edge Redirection on...

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13th International symposium on Quality electronic design (ISQED)

作者： Karputkin, Anton Ubar, Raimund Tombak, Mati Raik, Jaan Tallinn Univ Technol Tallinn Estonia

ISBN: (纸本)9781467310369;9781467310352

the paper presents a new method for design error correction by edge redirection on High-Level Decision Diagrams (HLDDs). In this paper, a canonical form of HLDDs developed by the authors is applied to automated correction of design errors. We show how realistic design errors can be represented by the redirection-based fault model. the theoretical basis of the approach is presented with the key advantages being the ability to handle multiple errors as well as the fact that the error correction is not restricted by the input stimuli. the method has been evaluated on a set of ITC99 benchmarks and on three real-world cores. Experiments show that the method is capable of correcting multiple design errors in very short run times

关键词： high level decision diagrams equivalence checking automated error correction

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thermal Via Structural design in three-Dimensional Integrated circuits

Thermal Via Structural Design in Three-Dimensional Integrate...

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13th International symposium on Quality electronic design (ISQED)

作者： Hwang, Leslie Lin, Kevin L. Wong, Martin D. F. Univ Illinois Coordinated Sci Lab Elect & Comp Engn 1101 W Springfield Ave Urbana IL 61801 USA Univ Illinois Urban Champaign Everitt Elect & Comp Engn Lab Elect & Comp Engn Urbana IL USA

ISBN: (纸本)9781467310369;9781467310352

3D IC, a novel packaging technology, is heavily studied to realize improved performance with denser packaging and reduced wirelength. Despite numerous advantages, thermal management is the biggest bottleneck to realize device stacking technology. In this paper, we propose a thermal-aware physical design for three-dimensional integrated circuits (3D IC). We aim to mitigate localized hotspots to ensure functionality by adding thermal fin geometry to existing thermal through silicon via (TTSV). We analyze various ways to insert thermal fin for single TTSV as well as TTSV cluster designs with the goal of maximizing heat dissipation while minimizing the interference with routing and area consumption. An analytical model of a three-dimensional system is developed and a thermal resistance circuit is built for accurate and time-efficient 3D thermal analysis.

关键词： thermal analysis 3D IC thermal fin TTSV finite element analysis

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Process Mismatch Analysis based on Reduced-Order Models

Process Mismatch Analysis based on Reduced-Order Models

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13th International symposium on Quality electronic design (ISQED)

作者： Yelten, Mustafa Berke Franzon, Paul D. Steer, Michael B. N Carolina State Univ Raleigh NC 27695 USA

ISBN: (纸本)9781467310369;9781467310352

this paper describes a methodology based on reduced-order models to investigate the effects of process mismatch in analog circuits in the presence of reliability degradation. Neural network-based reduced-order models for the DC drain current, I-ds, of 65 nm n- and p-channel transistors have been generated in terms of six process parameters, temperature, and device age. the models identify the contribution of process parameters to the mismatch of n- and p-channel transistors as they age. Hot carrier injection (HCI) is considered as the main reliability degradation for n-channel devices and negative bias temperature instability (NBTI) is considered for p-channel devices. It is demonstrated that the variations of the effective channel length and intrinsic threshold voltage are major contributors to device mismatch in the absence of aging. Finally, a beta multiplier current reference is analyzed using the developed models for the impact of process mismatch with and without the aging effects. It is shown that in a cascode current mirror the variability of the reference current can be reduced by ensuring that the same rail transistors experience similar variations.

关键词： Analog circuits mismatch analysis neural networks process variations reduced-order models reliability surrogate models

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