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检索条件"任意字段=13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

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On SAT-Based Model Checking of Speed-Independent circuits 25

On SAT-Based Model Checking of Speed-Independent Circuits

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25th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Huemer, Florian Najvirt, Robert Steininger, Andreas TU Wien Inst Comp Engn Vienna Austria

ISBN: (纸本)9781665494311

Formal verification plays an important role in the quality assurance of digital circuits. Apart from the now standard equivalence checking between design steps, functional correctness can be proven with model checking. In one approach, a Boolean satisfiability (SAT) problem describing the circuit's implementation and expected properties is generated for each of a bounded number of time steps and fed to a SAT solver. In synchronous circuits, the time steps correspond to cycles of the global clock. the execution of asynchronous, specifically speed-independent (SI) circuits, however, relies on local handshakes instead of a global time reference. this absence of a global clock requires a different approach for choosing time steps for the SAT problem. this paper presents how bounded, SAT-based model checking can be used on SI asynchronous circuits. We aim to give a general and accessible introduction to this topic, highlight the inherent computational complexity and show that setting up a basic model checker for SI circuits is possible with quite simple means, without any reliance on (expensive) commercial tools. For our reference implementation used in the provided examples we use the open source Z3 solver.

关键词： asynchronous speed-independent SAT bounded model checking

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PPA Based CNN Architecture Explorer 13

PPA Based CNN Architecture Explorer

引用

13th Latin America symposium on circuits and System (LASCAS)

作者： Shahshahani, Masoud Bhatia, Dinesh Univ Texas Dallas Dept Elect & Comp Engn Richardson TX 75080 USA

ISBN: (纸本)9781665420082

Field-Programmable Gate Arrays (FPGAs) are becoming increasingly popular for implementing convolutional neural networks (CNNs) due to their low latency and high energy efficiency. In practice, a software designer first explores various CNN architectures in software to improve architecture's validation accuracy. Once an architecture is finalized, the designer must build a computation core on an FPGA for inference acceleration. the requirement of FPGA Performance, Power consumption, and Area (or resources) (PPA) is affected by many CNN model parameters, accelerator topology, and classification accuracy for a CNN implementation. However, the CNN mapping design space is enormous, and efficient mapping of CNN can quickly become a challenging task. therefore, an exploration tool is essential for building a reconfigurable, fast, and efficient hardware accelerator. We have presented an integrated methodology for exploring FPGA-based CNN architectures by making tradeoffs between the performance, power, and area. this methodology becomes a mapping aid for software engineers who can evaluate the effect of CNN design on the implementation and performance of FPGA-based CNN accelerators.

关键词： FPGAs Accelerators Convolutional Neural Networks design Space Explorer

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Voltage-to-Voltage Sigmoid Neuron Activation Function design for Artificial Neural Networks 13

Voltage-to-Voltage Sigmoid Neuron Activation Function Design...

引用

13th Latin America symposium on circuits and System (LASCAS)

作者： Moposita, Tatiana Trojman, Lionel Crupi, Felice Lanuzza, Marco Vladimirescu, Andrei Sorbonne Univ ISEP Inst Super Elect Paris Paris France Univ Calabria DIMES Arcavacata Di Rende Italy

ISBN: (纸本)9781665420082

An Artificial Neural Network (ANN) involves a complex network of interconnected nodes called artificial neurons (AN);the AN sums N weighted inputs and send thought the result to a non-linear activation function (AF). In this work, a modified version of the sigmoid activation function is proposed. To obtain a voltage-to-voltage (V-V) transfer function required by an specific ANN. the proposed solution uses a pseudo-differential pair configuration at the input as voltage to current converter. the proposed circuit is designed using a commercial PDK in 180nm (TSMC) and is simulated in Virtuoso (Cadence). this specific design enable to obtain the desired steepness of the sigmoid function by means of the proper transistor sizing. Simulation results of our specific design show that we can reach an average relative error of only 1.09 % for steepness of 1 as compared to the exact mathematical function, and a power consumption of 6.77 mu W for steepness of 10.

关键词： Artificial Neural Network non-linear transfer function sigmoid activation function pseudo differential pair

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Hardware Obfuscation of Digital FIR Filters 25

Hardware Obfuscation of Digital FIR Filters

引用

25th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Aksoy, Levent Hepp, Alexander Baehr, Johanna Pagliarini, Samuel Tallinn Univ Technol Tallinn Estonia Tech Univ Munich Munich Germany

ISBN: (纸本)9781665494311

A finite impulse response (FIR) filter is a ubiquitous block in digital signal processing applications. Its characteristics are determined by its coefficients, which are the intellectual property (IP) for its designer. However, in a hardware efficient realization, its coefficients become vulnerable to reverse engineering. this paper presents a filter design technique that can protect this IP, taking into account hardware complexity and ensuring that the filter behaves as specified only when a secret key is provided. To do so, coefficients are hidden among decoys, which are selected beyond possible values of coefficients using three alternative methods. As an attack scenario, an adversary at an untrusted foundry is considered. A reverse engineering technique is developed to find the chosen decoy selection method and explore the potential leakage of coefficients through decoys. An oracle-less attack is also used to find the secret key. Experimental results show that the proposed technique can lead to filter designs with competitive hardware complexity and higher resiliency to attacks with respect to previously proposed methods.

关键词： hardware obfuscation IP protection reverse engineering oracle-less attack digital FIR filter design.

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Smart devices and RFID: towards an Android-based information system in the cattle-yards 13

Smart devices and RFID: towards an Android-based information...

引用

13th Latin America symposium on circuits and System (LASCAS)

作者： Sapriza, Juan Arnaud, Alfredo Bellini, Bruno Estevez, Felipe Miguez, Matias Univ Catolica Uruguay Av 8 Octubre 2738 Montevideo 11600 Uruguay BQN Technol Paysandu 1371 Montevideo 11200 Uruguay

ISBN: (纸本)9781665420082

the main change being observed in the use of Radio Frequency Identification (RFID) tools within the cattle industry is not related to the technology itself like hardware or protocols. Instead, is to incorporate RFID as part of the information system combined with a cattle database, not only to be compliant with mandatory traceability requirements, but also to increase productivity;the more on-site information the more efficiency to take decisions on individual animals. In this work, the evolution of a Low Frequency RFID (LF-RFID) stick reader named Baqueano from a simple traceability tool, towards the first Android RFID stick reader aimed at the cattle industry, is presented.

关键词： RFID circuits & systems for agribusiness Android devices

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Towards Polynomial Formal Verification of Complex Arithmetic circuits 25

Towards Polynomial Formal Verification of Complex Arithmetic...

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25th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Drechsler, Rolf Mahzoon, Alireza Goli, Mehran Univ Bremen Inst Comp Sci Bremen Germany DFKI GmbH Cyber Phys Syst Bremen Germany

ISBN: (纸本)9781665494311

With the growing demands for highly area-efficient, delay-optimized, and low-power designs, the complexity of digital circuits is increasing as well. Especially, a wide variety of arithmetic circuits, including different types of adders, multipliers, and dividers have been proposed to meet the demands in applications such as cryptography and Artificial Intelligence (AI). Some of these arithmetic circuits have highly parallel architectures and contain millions of gates;as a result, they are extremely errorprone. In the last 30 years, several formal verification methods have been proposed to verify arithmetic circuits. these methods report very good results when it comes to the verification of adders and structurally simple multipliers. Moreover, their space and time complexities are polynomial, i.e, they are scalable. However, when it comes to the verification of structurally complex multipliers, the story is different. In this paper, we investigate the space and time complexity of verifying a structurally complex multiplier using a word-level verification method. We prove that the space and time complexity is always exponential. then, we introduce a new verification strategy that takes advantage of several verification engines. We show that the polynomial formal verification of the complex multiplier becomes possible if the correctness of each stage is verified using the proper verification method. Our verification strategy can be applied to other complex digital circuits.

关键词： Logic gates Complexity theory Parallel architectures Time complexity Artificial intelligence Adders Digital circuits

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A Concept Towards Pressure-Controlled Microfluidic Networks 25

A Concept Towards Pressure-Controlled Microfluidic Networks

引用

25th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Fink, Gerold Hamidovic, Medina Haselmayr, Werner Wille, Robert Johannes Kepler Univ Linz Inst Integrated Circuits Linz Austria Johannes Kepler Univ Linz Inst Commun Engn & RF Syst Linz Austria Tech Univ Munich Chair Design Automat Munich Germany Software Competence Ctr Hagenberg GmbH SCCH Hagenberg Austria

ISBN: (纸本)9781665494311

Droplet-based microfluidic networks interconnect multiple microfluidic modules which allow to process (e.g., mix, sort, heat, incubate) so-called payload droplets (i.e., droplets containing a biological sample) on a single microfluidic chip. Inside such networks the path of a droplet and, thus, the module which processes it, can be controlled by microfluidic switches. thus far, these switches are realized by injecting additional control droplets into the network which allow to trigger the switching mechanism by solely exploiting passive hydrodynamic effects. While this eliminates the need of expensive components such as valves, this droplet-controlled switching concept is very sensitive and already slight deviations, e.g., in the control droplet injection could lead to incorrectly triggered switches. In this work, we address this issue by proposing a new concept of pressure-controlled networks which omit the control droplets (and their drawbacks) and, instead, use a single pump in order to drive the switches. Using design automation expertise together with established models, we derive a corresponding blueprint which realizes this idea for a specific network architecture. Simulations based on established methods and design tools confirmed the suitability of the proposed pressure-controlled networks.

关键词： Process control Switches Network architecture Control systems Valves Hydrodynamics design tools

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VLSI Architecture design Methodology for Deep learning based Upper Limb and Lower Limb Movement Classification for Rehabilitation Application 13

VLSI Architecture Design Methodology for Deep learning based...

引用

13th Latin America symposium on circuits and System (LASCAS)

作者： Nimbekar, Anagha Dinesh, Y. V. Sai Gautam, Arvind Hunsigida, Vidhumouli Nali, Appa Rao Acharyya, Amit IIT Hyderabad Dept Elect Engn Hyderabad 502285 Telangana India Xilinx Madhapur India

ISBN: (纸本)9781665420082

Recently, many works have proposed an highly accurate deep learning based movement classification algorithms for the assistive technology applications. But very less importance is given for it's corresponding hardward implementation. In this paper we proposed an VLSI architecture design methodology for deep learning based movement classification for assistive technology applications. LoCoMo-Net and MyoNet are the two Deep learning based networks proposed by Gautam et al [1] [2] for upper limb and lower limb for assistive technology. the proposed architecture is capable enough to adapt both the networks. We have implemented the architecture on ZYNQ ultra-scale + MPSoC zcu102 FPGA. LoCoMo-Net consumes 3.5 Watts of on chip power and MyoNet consumes 5 Watts of on chip power on the FPGA. LoCoMo-Net takes 1.876ms of time to classify the task and MyoNet takes 61.988ms of time to classify the task on FPGA.

关键词： Convolutional Neural Network (CNN) Long Short Term Memory (LSTM) LoCoMO-Net MyoNet sEMG movement classification

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design of a Miller Amplifier using gm/IDbased on A First-order Building Block Approximation 13

Design of a Miller Amplifier using gm/IDbased on A First-ord...

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13th International symposium on Advanced Topics in Electrical Engineering, ATEE 2023

作者： Palma, Victor Hugo Arzate Sandoval-Ibarra, Federico Cinvestav Department of Electronic Design Guadalajara Mexico

ISBN: (纸本)9798350331936

In this paper the gm/ID methodology for designing analog CMOS circuits is used. As a case of study the single-ended Miller OTA design is widely discussed and analized. In order to show the advantage of gm/ID it is demonstrated that the first order building block approximation allows to understand not only how to correctly do the sizing of each transistor, but also the physical meaning of each small-signal design model. this design flow is carried out by using design rules of a 130 nm CMOS technology, where Cadence is used for performing simulations at transistor level, obtaining results that confirm the usefullnes of the design models and the basics' veracity. © 2023 ieee.

关键词： Integrated circuit design

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Evaluating a Machine Learning-based Approach for Cache Configuration 13

Evaluating a Machine Learning-based Approach for Cache Confi...

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13th Latin America symposium on circuits and System (LASCAS)

作者： Ribeiro, Lucas Jacobi, Ricardo Junior, Francisco da Silva, Jones Yudi Silva, Ivan Saraiva Univ Brasilia Brasilia DF Brazil Univ Fed Piaui Teresina Piaui Brazil

ISBN: (纸本)9781665420082

As the systems perform progressively complex tasks, the search for energy efficiency in computational systems is constantly increasing. the cache memory has a fundamental role in this issue. through dynamic cache reconfiguration techniques, it is possible to obtain an optimal cache configuration that minimizes the impacts of energy losses. To achieve this goal, a precise selection of cache parameters plays a fundamental role. In this work, a machine learning-based approach is evaluated to predict the optimal cache configuration for different applications considering their dynamic instructions and a variety of cache parameters, followed by experiments showing that using a smaller set of application instructions it is already possible to obtain good classification results from the proposed model. the results show that the model obtains an accuracy of 96.19% using the complete set of RISC-V instructions and 96.33% accuracy using the memory instructions set, a more concise set of instructions that directly affect the cache power model, besides decreasing the model complexity.

关键词： Cache Memory design Dynamic Cache Reconfiguration Machine Learning Classification

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