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检索条件"任意字段=13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

共 683 条记录，以下是391-400 订阅

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Chip-Package Power Delivery Network Resonance Analysis and Co-design Using Time and Frequency Domain Analysis Techniques

Chip-Package Power Delivery Network Resonance Analysis and C...

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13th International symposium on Quality electronic design (ISQED)

作者： Watkins, Jonathan Pollayil, Jai Chow, Calvin Sarkar, Aveek Maxim Integrated Prod Inc Dallas TX USA Apache Design Inc San Jose CA 95134 USA

ISBN: (纸本)9781467310369;9781467310352

Traditional methods of performing worst-case DC or static analysis serves limited purposes for power delivery network (PDN) validation, especially when it comes to modeling chip-package-PCB coupling or resonance behavior. these methods do not consider the inductive and capacitive elements that dominate the chip and package interaction. they also fail to capture the impact of simultaneous switching current in creating local hot-spots and global voltage rail collapse. In this study, an analysis methodology that combines the use of both time and frequency domain techniques to model the impact of Ldi/dt noise and the coupling of chip-level switching current with chip-package impedance is presented. the outlined techniques were used on a design targeting high-speed signal processing applications to identify resonance behavior of chip-package PDN systems. Simulations were performed on various configurations of the design to ensure that the proposed design changes would correct the resonance and other PDN related issues. the analysis flow, information on the various data used, run-time and performance statistics, and the results from these experiments are presented.

关键词： PDN verification DC static AC transient

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design and Optimization of Power Gating for DVFS Applications

Design and Optimization of Power Gating for DVFS Application...

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13th International symposium on Quality electronic design (ISQED)

作者： Xu, Tong Li, Peng Texas A&M Univ Dept Elect & Comp Engn College Stn TX 77843 USA

ISBN: (纸本)9781467310369;9781467310352

Combined with dynamic voltage and frequency scaling (DVFS), power gating can be used effectively to improve the overall power efficiency of a chip design. Since the DVFS is applied to multiple supply voltage levels, the design tradeoffs between supply noise and power saving can vary significantly across different operating points. Hence, the tradeoffs have to be considered carefully by designers. In this paper, a systematic design tradeoff analysis for power gating geared towards DVFS applications is presented. We propose a multi-driver based scheme to drive sleep transistors. Re-routable decoupling capacitance based design strategies are used to balance supply noises and power saving at different supply levels. Finally, we demonstrate a simulation-based automatic design flow to improve the performance of power delivery network.

关键词： power-gating DVFS supply noise leakage saving

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A Scalable Curve-fit Model of the Substrate Coupling Resistances for IC design

A Scalable Curve-fit Model of the Substrate Coupling Resista...

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13th International symposium on Quality electronic design (ISQED)

作者： Gurugubelli, Vijaya Kumar Karmalkar, Shreepad Indian Inst Technol Dept Elect Engn Madras 600036 Tamil Nadu India

ISBN: (纸本)9781467310369;9781467310352

A new approach is presented for modeling the resistances of the substrate coupling network employed for noise calculations in the design of mixed-signal and RF ICs. the approach introduces intermediate resistances having progressively simpler current flow patterns than the coupling resistances. Each coupling resistance is then modeled as the product of two resistance ratios and a resistance having simple 1-D vertical or lateral flow, and each resistance ratio is approximated as a simple function of geometrical aspect ratios. Based on this approach, closed-form expressions are derived for coupling resistances associated with parallel stripe contacts on a substrate with or without a bottom contact, in terms of dimensions of the contact configuration and substrate parameters.

关键词： Closed-form modeling compact model substrate coupling resistance curve-fitting substrate noise

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NoC-based Platform for Embedded Software design: An Extension of the Hellfire Framework

NoC-based Platform for Embedded Software Design: An Extensio...

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13th International symposium on Quality electronic design (ISQED)

作者： Magalhaes, Felipe G. Longhi, Oliver Filho, Sergio J. Aguiar, Alexandra Hessel, Fabiano Pontificia Univ Catolica Rio Grande do Sul Fac Informat Porto Alegre RS Brazil

ISBN: (纸本)9781467310369;9781467310352

this paper presents an extension of the Hellfire Framework (HFFW), providing an intuitive and powerful web interface to build, test and debug a complete Multiprocessor System-on-Chip (MPSoC). Among the new functionalities presented, it is possible to highlight: i) the architecture builder tool, used to set up all the MPSoC architecture;ii) the possibility to use a Network-on-Chip (NoC) as the communication mean, and;iii) a new simulator, providing a fast and accurate high level Instructions Set Simulator (ISS) with a miss ratio less than 5%. In order to validate the new simulator accuracy several tests were taken, first using traffic generators and then an implementation of the Secure Hash Algorithm (SHA). the achieved results are discussed throughout the paper.

关键词： MPSoC NoC Instruction Set Simulator

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design Issues and Insights of Multi-Fin Bulk Silicon FinFETs

Design Issues and Insights of Multi-Fin Bulk Silicon FinFETs

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13th International symposium on Quality electronic design (ISQED)

作者： Li, Hsun Chiang, Meng-Hsueh Department of Electronic Engineering National Ilan University Taiwan

ISBN: (纸本)9781467310369

Multi-fin bulk silicon FinFET-based design issues and implications using 3D numerical simulation are presented for the first time. In order to gain sufficient drive current of each transistor, multi-fin layout is inevitable due to limited aspect ratio or fin height. However, how the multi-fin design impacts the circuit performance needs to be taken into account. Because of non-planar nature of the fin, conventional concept of multi-finger design in bulk CMOS technology does not apply. We found an extra leakage path underneath the fin spacing between source and drain. Such impact can be mitigated by additional substrate doping and proper gate-to-substrate isolation. Based on the proposed design window at a tight pitch control, good performance can be achieved while meeting leakage current requirement.

关键词： Bulk FinFET multi-fin fin pitch isolation oxide

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Radiation-tolerant combinational gates - An implementation based comparison

Radiation-tolerant combinational gates - An implementation b...

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2012 ieee 15th International symposium on design and diagnostics of electronic circuits and systems, DDECS 2012

作者： Savulimedu Veeravalli, Varadan Steininger, Andreas Institute of Computer Engineering Vienna University of Technology Vienna Austria

ISBN: (纸本)9781467311854

As newer CMOS technologies are known to be more susceptible to particle hits, radiation tolerance is receiving increased attention. Several techniques for attaining this property are available in the literature already. However, virtually all of the publications refer to an inverter circuit, and the related robustness assessments (if any) are hard to compare, since important characteristics, such as technology or fault model, differ. In this paper we fill this gap by applying the available concepts to combinational gates, in particular an XOR gate, using the same concrete technology and sizing as well as the same fault model. By means of extensive analog simulations we verify and finally tune their robustness to the same level. On this foundation we can then make a comparison of the respective overheads and problems, such that it becomes relatively easy to distinguish efficient solutions from problematic ones. © 2012 ieee.

关键词： INVERTER circuits Analog simulation exclusive or gate gates CMOS technology Radiation Tolerance CONCRETE TECHNOLOGY

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DRC-Free High Density Layout Exploration with Layout Morphing and Patterning Quality Assessment, with Application to SRAM

DRC-Free High Density Layout Exploration with Layout Morphin...

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13th International symposium on Quality electronic design (ISQED)

作者： Singhee, Amith Acar, Emrah Younus, Mohammad I. Singh, Rama N. Bansal, Aditya IBM TJ Watson Res Ctr Yorktown Hts NY 10598 USA IBM Semicond Res & Dev Ctr East Fishkill NY USA

ISBN: (纸本)9781467310369;9781467310352

A system for layout exploration without design-rule checking is presented. It comprises of two key and new capabilities: 1) layout morphing to generate multi-mask layer layout variants, given basis layouts, and 2) feature-driven layout quality evaluation using through-process patterning simulations. the former uses morphing techniques inspired from image processing. the latter uses design-specific marker shapes to identify relevant features and efficient geometric operations on the simulated contours and these markers. the methodology is useful for high-density layout design and design rule development where design rules are insufficient or irrelevant, especially at 22 nm technology and beyond. We demonstrate it on an aggressive 22 nm SRAM bitcell design.

关键词： Layout physical design lithography simulation morphing

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Optimal Microarchitectural design Configuration Selection for Processor Hard-Error Reliability

Optimal Microarchitectural Design Configuration Selection fo...

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13th International symposium on Quality electronic design (ISQED)

作者： Zhang, Ying Duan, Lide Li, Bin Peng, Lu Louisiana State Univ Dept Elect & Comp Engn Baton Rouge LA 70803 USA Louisiana State Univ Dept Expt Stat Baton Rouge LA 70803 USA

ISBN: (纸本)9781467310369;9781467310352

Traditional design space exploration mainly focuses on performance and power consumption. However, as one of the first-class constraints for modern processor design, the relationship between hard-error reliability and processor configurations has not been well studied. In this paper, we investigate this relationship by exploring a large processor design space. We employ a rule search strategy, i.e. Patient Rule Induction Method, to generate a set of rules which choose optimal configurations for processor hard-error reliability and its tradeoff with performance and power consumption.

关键词： design space exploration reliability statistical model

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Test Structure, circuits and Extraction Methods to Determine the Radius of Infuence of STI and Polysilicon Pattern Density

Test Structure, Circuits and Extraction Methods to Determine...

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13th International symposium on Quality electronic design (ISQED)

作者： Chang, Albert H. Zuo, Kewei Wang, Jean Yu, Douglas Boning, Duane MIT Microsyst Technol Labs Cambridge MA 02139 USA Taiwan Semicond Mfg Co Ltd Hsinchu Taiwan

ISBN: (纸本)9781467310369;9781467310352

Advanced CMOS processes need new methodologies to extract, characterize and model process variations and their sources. Most prior studies have focused on understanding the effect of local layout features on transistor performance;limited work has been done to characterize medium-range (approximate to 10 mu m to 2mm) pattern density effects. We propose a new methodology to extract the radius of influence, or the range of neighboring layout that should be taken into account in determining transistor characteristics, for shallow trench isolation (STI) and polysilicon pattern density. A test chip, with 130k devices under test (DUTs) and step-like pattern density layout changes, is designed in 65nm bulk CMOS technology as a case study. the extraction result of the measured data suggests that the local layout geometry, within the DUT cell size of 6 mu m x 8 mu m, is the dominant contributor to systematic device variation. Across-die medium-range layout pattern densities are found to have a statistically significant and detectable effect, but this effect is small and contributes only 2-5% of the total variation in this technology.

关键词： Polysilicon

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Transaction-Based Post-Silicon Debug of Many-Core System-on-Chips

Transaction-Based Post-Silicon Debug of Many-Core System-on-...

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13th International symposium on Quality electronic design (ISQED)

作者： Gharehbaghi, Amir Masoud Fujita, Masahiro Univ Tokyo VLSI Design & Educ Ctr Tokyo Japan

ISBN: (纸本)9781467310369;9781467310352

this paper presents a post-silicon debug method for many-core systems that focuses on the transactions among the cores. For each core, we extract a finite state machine that represents its abstracted behavior in terms of communication with other cores. Debugging is performed on the execution paths that are generated by traversing multiple state machines of the cores using the transactions that are monitored at run-time. First, we start from the last state of a core-under-debug and provide possible previous states according to the monitored communication behavior of the core. this process is repeated, and a number of possible execution paths are generated. Next, we analyze more detailed behavior of each state over the generated paths using a bounded model checker and also designers' assertions. this way, we eliminate the infeasible paths as well as finding the constraints on internal variables of the cores that has lead to an error. To show the effectiveness of our method, we have used a distributed deadlock detection and resolution algorithm that is implemented on top of a network-on-chip (NoC) as a case study. We show that using our method, we can successfully backtrack in states of multiple cores in the system as well as finding bugs.

关键词： post-silicon debug system-level design bounded model checking system-on-chip (SoC) network-on-chip (NoC)

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