检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

665 篇 会议
18 篇 期刊文献

馆藏范围

683 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

472 篇 工学
- 398 篇 电气工程
- 185 篇 电子科学与技术（可...
- 151 篇 计算机科学与技术...
- 24 篇 材料科学与工程（可...
- 16 篇 软件工程
- 8 篇 机械工程
- 7 篇 信息与通信工程
- 7 篇 控制科学与工程
- 4 篇 交通运输工程
- 3 篇 安全科学与工程
- 2 篇 动力工程及工程热...
- 2 篇 建筑学
- 2 篇 土木工程
- 2 篇 化学工程与技术
- 2 篇 网络空间安全
- 1 篇 力学（可授工学、理...
- 1 篇 仪器科学与技术
- 1 篇 林业工程
13 篇 理学
- 7 篇 数学
- 5 篇 物理学
- 3 篇 系统科学
- 1 篇 统计学（可授理学、...
6 篇 管理学
- 5 篇 管理科学与工程(可...
- 1 篇 图书情报与档案管...

主题

36 篇 hardware
31 篇 field programmab...
30 篇 circuit faults
29 篇 cmos integrated ...
22 篇 logic gates
21 篇 integrated circu...
21 篇 clocks
20 篇 digital circuits
19 篇 reliability
19 篇 circuit testing
19 篇 algorithm design...
19 篇 delay
19 篇 cmos technology
17 篇 power demand
17 篇 electronic circu...
16 篇 timing circuits
15 篇 analog circuits
15 篇 fpga
14 篇 hardware design ...
14 篇 optimization

机构

12 篇 faculty of infor...
8 篇 univ bremen inst...
8 篇 brno univ techno...
7 篇 slovak univ tech...
6 篇 ihp technol pk 2...
5 篇 institute of com...
5 篇 univ oslo dept i...
5 篇 warsaw univ tech...
4 篇 ihp im technolog...
4 篇 univ tokyo vlsi ...
4 篇 univ manchester ...
4 篇 dfki gmbh cyber ...
4 篇 brno univ techno...
4 篇 silesian tech un...
4 篇 infineon technol...
4 篇 st microelect gr...
4 篇 norwegian univer...
4 篇 warsaw univ tech...
4 篇 ihp
3 篇 johannes kepler ...

作者

12 篇 sekanina lukas
11 篇 stopjakova viera
11 篇 pleskacz witold ...
10 篇 drechsler rolf
10 篇 asada kunihiro
8 篇 rolf drechsler
8 篇 steininger andre...
8 篇 kerkhoff hans g.
7 篇 kubatova hana
7 篇 krstic milos
7 篇 raik jaan
7 篇 ubar raimund
7 篇 bosio alberto
7 篇 vierhaus heinric...
7 篇 borejko tomasz
6 篇 arbet daniel
6 篇 siwiec krzysztof
6 篇 viera stopjakova
6 篇 nakura toru
6 篇 klaus hofmann

语言

682 篇 英文
1 篇 中文

检索条件"任意字段=13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

共 683 条记录，以下是411-420 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Effcient Approaches to Overcome Non-Convexity Issues in Analog design Automation

Effcient Approaches to Overcome Non-Convexity Issues in Anal...

引用

13th International symposium on Quality electronic design (ISQED)

作者： Maji, Supriyo Mandal, Pradip Indian Inst Technol Dept Elect & Elect Commun Engn Kharagpur 721302 W Bengal India

ISBN: (纸本)9781467310369

We propose two approaches to overcome limitation of convex programming technique for analog design automation. Analog design performance constraints are cast in posynomial inequality format for suitability into convex optimization based application. But in most cases original equations are not in posynomial so, either they are deliberately modeled or approximated. this leads to inaccuracy. Our first approach is based on exploiting apparent benefit of convex programming based global optimizer but still making use of highly accurate non-posynomial or signomial model. To achieve that, we combine both global and local optimizer. Global optimizer handles less accurate posynomial equation ensuring global optimality. And the initial guess obtained therefore is used by local optimizer to handle accurate signomial model. Second approach demonstrates that the targeted region to be modeled for circuit sizing can be reduced which invariably leads to better model accuracy. We develop low dropout regulator (LDO) performance metrics in posynomial and signomial format for use in the proposed methodology.

关键词： convex programming Computer-Aided design Analog Analog Handles

来源：评论

学校读者我要写书评

暂无评论

Process Variation Tolerant 9T SRAM Bitcell design

Process Variation Tolerant 9T SRAM Bitcell Design

引用

13th International symposium on Quality electronic design (ISQED)

作者： Reddy, G. K. Jainwal, Kapil Singh, Jawar Mohanty, Saraju P. Jaypee Univ Engn & Technol Dept Elect & Commun Engn Raghogarh India Ind Inst Informat Technol Design & Mfg Dept Elect & Commun Engn Jabalpur India Univ North Texas Dept Comp Sci & Engn Denton TX 76203 USA

ISBN: (纸本)9781467310369;9781467310352

In this paper, a nine-transistor (9T) Static Random Access Memory (SRAM) bitcell for the low voltage and energy constraint applications is proposed. It is well known that in sub-threshold regime, reliability and process variations are the main design challenges, and standard six-transistor (6T) SRAM bitcell fails to operate in sub-V-th. the proposed design has better read stability and improved process variation tolerant as compared to standard 6T SRAM at low voltage. Simulation results based on 32nm technology node shows that there is 37% improvement in the read stability as compared to standard 6T SRAM bitcell. the proposed design also address the conflicting read and write requirements, therefore, one can optimize the read static noise margin (SNM), write noise margin and write speed for a particular application by selecting the bitcell ratios for read and write operations.

关键词： process change Static random access storage Low voltage write operation

来源：评论

学校读者我要写书评

暂无评论

Robust Metastability-based TRNG design in Nanometer CMOS with Sub-Vdd Pre-charge and Hybrid Self-calibration

Robust Metastability-based TRNG Design in Nanometer CMOS wit...

引用

13th International symposium on Quality electronic design (ISQED)

作者： Suresh, Vikram B. Burleson, Wayne P. Univ Massachusetts Dept Elect & Comp Engn Amherst MA 01003 USA

ISBN: (纸本)9781467310369;9781467310352

In this work, we study the impact of sub-vdd pre-charge operation of metastability-based True Random Number Generator (TRNG) and propose a hybrid self-calibration to improve the statistics of the TRNG in the presence increasing intra-die variation. circuits designed in deep submicron technologies are susceptible to process variation. the variability may affect the circuit performance, power and reliability. Numerous pre-silicon design methodologies and post-silicon circuit tuning mechanisms have been studied in literature. We propose a sub-vdd pre-charge technique to improve the tolerance of the TRNG to device mismatch. this is followed by a hybrid self-detection and calibration technique based on algorithmic post processing and circuit tuning to mitigate the effects of variability. the cryptographic metric of 'bit entropy' is used to validate the proposed techniques. the TRNG circuit and the proposed techniques are implemented using 45nm PDK. Results show that variation in fabrication process affect the reliability of TRNG circuits. Pre-charging the TRNG to 0.7V for a typical supply voltage of 1.1V reduces the impact of device mismatch on the circuit by 2X for device mismatch as large as 4-5%. the hybrid self-calibration further improves the bit entropy by similar to 120% across a range of 5% intra-die variation. the simple control logic has an estimated area of 128 um(2) and results in a negligible energy overhead of 0.82 fJ/bit.

关键词： TRNG Intra-die variation Entropy Hybrid Self-calibration

来源：评论

学校读者我要写书评

暂无评论

Metamodel-Assisted Ultra-Fast Memetic Optimization of a PLL for WiMax and MMDS Applications

Metamodel-Assisted Ultra-Fast Memetic Optimization of a PLL ...

引用

13th International symposium on Quality electronic design (ISQED)

作者： Garitselov, Oleg Mohanty, Saraju P. Kougianos, Elias Okobiah, Oghenekarho Univ N Texas NanoSyst Design Lab Denton TX 76203 USA

ISBN: (纸本)9781467310369;9781467310352

With CMOS technologies progressing deeper into the nano-scale domain the design of analog and mixed-signal components is becoming very challenging. the presence of parasitics and the complexity of calculations involved create an enormous challenge for designers to keep their design within specifications when reaching the physical layout stage of the design process. this paper proposes a novel ultra-fast design flow that uses memetic-based optimization algorithms over neural-network based non-polynomial metamodels for design-space exploration. A new heuristic optimization algorithm which is based on memetic algorithms and artificial bee colony optimization is introduced. the design flow relies on a multiple-layer feed-forward neural network metamodel of the nano-CMOS circuit. Using a CMOS PLL circuit it is shown that the proposed design flow is flexible and robust while it achieves optimal design to two different wireless specifications, WiMax and MMDS. Experimental results show that the proposed approach is 2.4x faster than the swarm based optimization over the same metamodels.

关键词： Metamodeling Neural Networks Memetic Nano-CMOS PLL Modeling Circuit Optimization

来源：评论

学校读者我要写书评

暂无评论

Low Complexity Cross Parity Codes for Multiple and Random Bit Error Correction

Low Complexity Cross Parity Codes for Multiple and Random Bi...

引用

13th International symposium on Quality electronic design (ISQED)

作者： Poolakkaparambil, Mahesh Mathew, Jimson Jabir, Abusaleh M. Mohanty, Saraju P. Oxford Brookes Univ Dept Comp Sci & Elect Oxford OX3 0BP England Univ Bristol Dept Comp Sci Bristol BS8 1TH Avon England Univ North Texas Dept Comp Sci & Engn Denton TX 76203 USA

ISBN: (纸本)9781467310369;9781467310352

Error detection and correction which has been used in communication and memory design is becoming increasingly important in fault tolerant logic circuit design. As a result of the aggressive technology scaling, the current high-density integrated circuits are easily succumbed to faulty operations generated from many sources including stuck-at-faults, radiation induced faults, or malicious eavesdropper attacks. the currently used techniques like low-density parity-check (LDPC) and Hamming code based fault masking to mitigate bit flips in the digital circuits are either single bit error correcting or multiple error correctable with Bose-Choudhury-Hocquenghem (BCH) and Reed-solomon based methods with very large overheads. this paper introduce a novel cross code based method that can correct multiple errors with minimal compromise in error correction capability and area. the key idea of the novel method proposed in this paper is that do not correct all the errors but minimize their probability being escaped. Experimental results of the proposed methods show that the following: (1) area overhead is 101% for Hamming cross code and 106% for BCH cross code for a 90-bit finite field multiplier and (2) 150% for Hamming cross code and 170% for BCH cross codes for practically used 163-bit digit serial polynomial basis multiplier. thus, the proposed methods are significantly efficient compared to Triple Modular Redundancy (TMR), LDPC, Hamming based methods in terms of area overhead and also the first attempted approach to a low complexity multiple error correctable digit serial multiplier to the best of the authors knowledge.

关键词： Polynomial Basis Bultiplier Concurrent Error Detection Single Error Correction N-Modular Redundancy Bose-Choudhury-Hocquenghem Code

来源：评论

学校读者我要写书评

暂无评论

Physical-design-Friendly Hierarchical Logic Built-In Self-Test - A Case Study

Physical-Design-Friendly Hierarchical Logic Built-In Self-Te...

引用

13th International symposium on Quality electronic design (ISQED)

作者： Nelson, Kelvin Shanmugavadivelu, Jaga Mekkoth, Jayanth Ghanta, Venkat Wu, Jun Zhuang, Fe Chao, Hao-Jan Wu, Shianling Rao, Jie Yu, Lizhen Wang, Laung-Terng Cisco Syst 175 W Tasman Dr San Jose CA 95134 USA Cisco Syst Shanghai Peoples R China SynTest Technol Sunnyvale CA 94086 USA

ISBN: (纸本)9781467310369;9781467310352

this paper describes an application of a physical-design-friendly hierarchical logic built-in self-test (BIST) architecture and validation methodology on a networking system-on-chip (SOC) design. the design consists of two embedded cores, each containing approximately 45 million primitives and 2.5 million flip-flops. the implemented architecture supports an at-speed staggered launch-on-capture clocking scheme and includes novel features to reduce turnaround time during engineering change order (ECO) and the device's BIST runtime. It also embeds test and diagnosis features to facilitate debugging of the device at the system level. the BIST hierarchy includes wrappers surrounding each core with access from chip-top allowing for both parallel and serial validations of the cores. this case study successfully demonstrates the feasibility of using the implemented features for speedy ECO, synergy with physical design flow, and ease of test and diagnosis.

关键词： Logic BIST launch-on-capture BIST diagnosis

来源：评论

学校读者我要写书评

暂无评论

design of an Efficient NoC Architecture using Millimeter-Wave Wireless Links

Design of an Efficient NoC Architecture using Millimeter-Wav...

引用

13th International symposium on Quality electronic design (ISQED)

作者： Deb, Sujay Chang, Kevin Ganguly, Amlan Yu, Xinmin Teuscher, Christof Pande, Partha Heo, Deukhyoun Belzer, Benjamin Washington State Univ Pullman WA 99164 USA Rochester Inst Technol Rochester NY USA Portland State Univ Portland OR USA

ISBN: (纸本)9781467310369;9781467310352

the Network-on-Chip (NoC) is an enabling technology to integrate large numbers of embedded cores on a single die. Traditional multi-core designs based on the NoC paradigm suffer from high latency and power dissipation due to the inherent multi-hop nature of communication. the performance of NoC fabrics can be significantly enhanced by introducing long-range, low power, and high-bandwidth single-hop links between far apart cores. In this paper we present a design methodology and performance evaluation for a hierarchical small-world NoC with on-chip millimeter (mm)-wave wireless channels as long-range communication links. the proposed wireless NoC offers significantly better performance in terms of achievable bandwidth and energy dissipation compared to its conventional multi-hop wired counterpart in both uniform and non-uniform traffic scenarios. the performance improvement is achieved through efficient data routing, an optimum placement of the wireless hubs, and an energy-efficient transceiver design.

关键词： Networks on Chip Wireless Small-world

来源：评论

学校读者我要写书评

暂无评论

History & Variation Trained Cache (HVT-Cache): A Process Variation Aware and Fine Grain Voltage Scalable Cache with Active Access History Monitoring

History & Variation Trained Cache (HVT-Cache): A Process Var...

引用

13th International symposium on Quality electronic design (ISQED)

作者： Sasan, Avesta Homayoun, Houman Amiri, Kiarash Eltawil, Ahmed Kudahi, Fadi Univ Calif Irvine Dept Elect & Comp Engn Irvine CA 92717 USA Univ Calif San Diego Dept Comp Sci & Engn San Diego CA USA

ISBN: (纸本)9781467310369;9781467310352

Process variability and energy consumption are the two most formidable challenges facing the semiconductor industry nowadays. To combat these challenges, we present in this paper the "History and Variation Trained-Cache" (HVT-Cache) architecture. HVT-Cache enables fine grain voltage scaling within a memory bank by taking into account both memory access pattern and process variability. the supply voltage is changed with alterations in the memory access pattern to maximize power saving, while assuring safe operation (read and write) by guarding against process variability. In a case study, SimpleScalar simulation of the proposed 32KB cache architecture reports over 40% reduction in power consumption over standard SPEC2000 integer benchmarks while incurring an area overhead below 4% and an execution time penalty smaller than 1%.

关键词： Low power memory design process variation low power voltage scaling reconfigurable cache process variation aware cache

来源：评论

学校读者我要写书评

暂无评论

Critical Area Driven Dummy Fill Insertion to Improve Manufacturing Yield

Critical Area Driven Dummy Fill Insertion to Improve Manufac...

引用

13th International symposium on Quality electronic design (ISQED)

作者： Dhumane, Nishant Kundu, Sandip Univ Massachusetts ECE Dept Amherst MA 01003 USA

ISBN: (纸本)9781467310369;9781467310352

Non-planar surface may cause incorrect transfer of patterns during lithography. In today's IC manufacturing, chemical mechanical polishing (CMP) is used for topographical planarization. Since polish rates for metals and oxides are different, dummy metal fills in layout is used to minimize post-CMP thickness variability. Existing metal fill solutions target secondary goals minimizing timing and crosstalk impact. they may however reduce yield by increasing probability of failure (POF) due to particulate defects. Layout design solutions that minimize POF and also improve surface planarity via dummy fill insertions have competing requirements for line spacing. In this work, we present a formulation to balance these competing goals and provide a comparative study of greedy (or fixed spacing), variable spacing and LP formulation based fill insertions based on scalability and quality of solution. Finally, we extend the critical area based solution to include SRAF insertion in order to account for optical diffraction in lithography. the key contributions of this paper are i) layout density analysis model, ii) heuristic greedy, variable spacing and LP formulation based fill insertion techniques and iii) characterization and implementation of inter-feature spacing based SRAF insertion. thus the proposed solution addresses both lithography and particulate related defects. Experimental results based on layout of ISCAS 85 benchmark circuits show that the variable spacing and the LP formulation based fill insertion techniques result in substantially reduced critical area while satisfying the layout density and uniformity criteria.

关键词： design for Manufacturability (DFM) Chemical-Mechanical Polishing (CMP) Dummy fill Critical Area Analysis Layout density

来源：评论

学校读者我要写书评

暂无评论

Understanding, Modeling, and Detecting Pooling Hotspots in Copper CMP

Understanding, Modeling, and Detecting Pooling Hotspots in C...

引用

13th International symposium on Quality electronic design (ISQED)

作者： Gower-Hall, Aaron Gbondo-Tugbawa, Tamba Weng, JenPin Tseng, Wei-tsu Economikos, Laertis Yanagisawa, Toshiaki Bashaboina, Pavan Greco, Stephen Cadence Design Syst San Jose CA 94088 USA IBM Semicond Res & Dev Ctr Hopewell Jct NY 12533 USA

ISBN: (纸本)9781467310369;9781467310352

Multi-step Chemical Mechanical Polishing (CMP) has been used in copper interconnect fabrication for more than a decade. During this time, advances in both the CMP-based damascene manufacturing processes and in the design flows, have enabled significant uniformity improvements for both metal thickness and surface topography, producing corresponding improvements in parametric and functional yields and enabling smaller process nodes. However, improving post CMP planarity and widening CMP process windows have lead to an increased risk of functional yield failures due to copper pooling (sometimes called puddling). these failures occur when the overburden copper and/or barrier material is not cleared during CMP, producing an electrical short between two neighboring lines. We first sought to understand the source of this failure mode, based on recently reported research and data trends seen in state of the art copper CMP manufacturing processes. Once copper pooling mechanisms were identified, CMP models were enhanced to more accurately predict pooling hotspot locations. these models can be used to improve CMP process optimization and/or design for Manufacturing (DFM) based flows that detect and remove pooling hotspots.

关键词： Chemical Mechanical Polishing (CMP) Copper Pooling (Puddling) design for Manufacturability (DFM)

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共69页 << < 38 39 40 41 42 43 44 45 46 47 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：