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检索条件"任意字段=13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

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theory of Redundancy for Logic circuits to Maximize Yield/Area

Theory of Redundancy for Logic Circuits to Maximize Yield/Ar...

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13th International symposium on Quality electronic design (ISQED)

作者： Mirza-Aghatabar, Mohammad Breuer, Melvin A. Gupta, Sandeep K. Nazarian, Shahin Univ So Calif Ming Hsieh Dept Elect Engn Los Angeles CA 90089 USA

ISBN: (纸本)9781467310369;9781467310352

the down scaling of feature sizes and higher process variations in future CMOS nano-technologies are anticipated to introduce higher manufacturing anomalies. On the other hand designs are getting more complicated due to more innovative applications where they need higher numbers of transistors. these phenomena significantly reduce the functional yield. Redundancy has been used for a long time in regular structures such as memory to tolerate defects;however, for typical irregular logic circuits this would be very challenging. In this paper we introduce a theory that justifies the necessity of using redundancy at sub-chip level of granularity to maximize yield/area (number of healthy dies) for future technologies with higher defect rates. In addition, redundancy at finer levels of granularity, aggravates the overheads of interconnect (steering logics, i.e., forks, joins and switches) such as yield, area, and testing overheads. these overheads limit the level of granularity for logic replication. Current yield estimators are generally pessimistic for interconnects because they do not take circuit and logic context into consideration, and/or they assume all defects are killer-defects, i.e., always result in unacceptable circuit behavior. In this paper we propose a CAD tool to compute the functional yield of the configurable and testable steering logics using (i) actual layout geometries, and (ii) factory data related to density and size of opens (missing metal), shorts (extra metal) and open vias. the experimental results show that our theory of redundancy considering the overheads of steering logics can improve the yield/area by 2.8 times for a real highly-defected circuit (OpenSparc T2 core).

关键词： Yield redundancy steering logics CAD tool layout

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Process Variation Aware DRAM design Using Block Based Adaptive Body Biasing Algorithm

Process Variation Aware DRAM Design Using Block Based Adapti...

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13th International symposium on Quality electronic design (ISQED)

作者： Desai, Satyajit Roy, Sanghamitra Chakraborty, Koushik Utah State Univ Logan UT 84322 USA

ISBN: (纸本)9781467310369;9781467310352

Large dense structures like DRAMs are particularly susceptible to process variation, which can lead to variable latencies in different memory arrays. However, very little work exists on variation studies in the DRAM. this is due to the fact that DRAMs were traditionally placed off-chip and their latency changes due to process variation did not impact the overall processor performance. However, emerging technology trends like three dimensional integration, use of sophisticated memory controllers and continued scaling of technology nodes, substantially reduces DRAM access latency. Hence future technology nodes will see widespread adoption of embedded DRAMs. this makes process variation a critical upcoming challenge in DRAMs that must be addressed in current and forthcoming technology generations. In this paper, we present techniques for modeling the effect of random as well as spatial variation in large DRAM array structures. We use sensitivity based gate level process variation models combined with statistical timing analysis to estimate the impact of process variation on the DRAM performance and leakage power. We also propose a simulated annealing based Vth assignment algorithm using adaptive body biasing to improve the yield of DRAM structures. Applying our algorithm on a 1GB DRAM array, we report an average of 10.3% improvement in the DRAM yield. To the best of our knowledge, ours is the first technique to model the imp act of process variation on large scale DRAM arrays.

关键词： Process Variation DRAM Adaptive body bias

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design of Low-Power, Scalable-throughput systems at Near/Sub threshold Voltage

Design of Low-Power, Scalable-Throughput Systems at Near/Sub...

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13th International symposium on Quality electronic design (ISQED)

作者： Srivastav, Meeta Henry, Michael B. Nazhandali, Leyla Virginia Tech Bradley Dept Elect & Comp Engn Blacksburg VA 24060 USA

ISBN: (纸本)9781467310369;9781467310352

Voltage scaling has been a prevalent method of saving energy for energy constrained applications. However, voltage scaling along with shrinking process technologies exacerbate process variation effects on transistor. Large variation in transistor parameters, result in high variation in performance and power across the chip. these effects if ignored at the stage of designing will result into unpredictable behavior when deployed in the actual field. In this paper, we leverage the benefits of voltage scaling methodology for obtaining energy efficiency and compensate for the loss in throughput by exploiting parallelism present in the various DSP designs. To achieve scalable throughput, we depend on both dynamic voltage scaling with a few operating voltage options and active unit scaling, where the number of active parallel units is reduced using power gating. We show that such hybrid method consumes 8%-77% less power compared to simple dynamic voltage scaling over different throughputs. We study this system architecture in two different workload environments, one static and one dynamic. In the former, the desired target throughput is predetermined and fixed and in the latter, it can be changed dynamically. We show that to achieve highest level of energy efficiency, the number of cores and the operating voltages vary widely between a base designs versus a process variation aware (PVA) design. We further show that the PVA design enjoys an average of 26.9% and 51.1% reduction in energy consumption for the static and dynamic designs respectively over six different DSP applications. this is because the base design needs to compensate for the effects of process variation as an after fact, while the PVA is able to make suitable decisions at the time of the design.

关键词： Process variation Low-power Active-unit-scaling Voltage scaling DSP PTM 45nm Energy

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High Performance Electrical Driven Hotspot Detection Solution for Full Chip design using a Novel Device Parameter Matching Technique

High Performance Electrical Driven Hotspot Detection Solutio...

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13th International symposium on Quality electronic design (ISQED)

作者： Salem, Rami F. Al-Imam, Mohamed ElMously, Abdelrahman Eissa, Haitham Arafa, Ahmed Anis, Mohab H. Mentor Graphics Corporation United States American University Cairo Egypt

ISBN: (纸本)9781467310369

With the continuous development of today's technology, IC design becomes a more complex process. the designer now not only takes care of the normal design and layout parameters as usual, but also needs to consider the process variation impact on the design to preserve the same chip functionality with no failure during fabrication. In the current process, schematic designers go through extensive simulations to cover all the possible variations of their design parameters and hence of the design functionality. At the same time, layout designers perform time-consuming process-aware simulations (such as lithography simulations) on the full chip layout, which impacts the design turn-around time. In this paper, we present a fast physical layout- and electrical-aware design-For-Manufacturability (DFM) solution that detects hotspot areas in the full chip design without requiring extensive electrical and process simulations. Novel algorithms are proposed to implement the engines that are used to develop this solution. Our proposed flow is examined on a 45 nm industrial Finite Impulse Response (FIR) full chip. the proposed methodology is able to define a list of electrical hotspot devices located on the FIR critical path that experience up to 17% variation in their DC current values due to the effect of process and design context. the total runtime needed to identify and detect these electrical hotspots on the FIR full chip takes nearly 3 minutes, compared to hours when using conventional electrical and process simulations.

关键词： Process variations design-For-Manufacturability (DFM) Lithography variations Stress effects Electrical design-For-Manufacturability (e-DFM) Parametric Yield Hot spots

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DDRO: A Novel Performance Monitoring Methodology Based on design- Dependent Ring Oscillators

DDRO: A Novel Performance Monitoring Methodology Based on De...

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13th International symposium on Quality electronic design (ISQED)

作者： Chan, Tuck-Boon Gupta, Puneet Kahng, Andrew B. Lai, Liangzhen Univ Calif San Diego ECE Dept La Jolla CA 92093 USA Univ Calif San Diego CSE La Jolla CA 92093 USA Univ Calif Los Angeles EE Dept Los Angeles CA 90095 USA

ISBN: (纸本)9781467310369;9781467310352

As CMOS technology scales, circuit performance becomes more sensitive to manufacturing and environmental variations. Hence, there is a need to measure or monitor circuit performance during manufacturing and at runtime. Since each circuit may have different sensitivities to process variations, previous works have focused on synthesis of circuit performance monitors that are specific to a given design. In this work, we study the potential benefit of having multiple design-dependent monitors. We develop a systematic approach to the synthesis of multiple design-dependent monitors, as well as a corresponding delay estimation method. Our approach synthesizes design-dependent ring oscillators (DDROs) using standard library gates. this has the advantage of quick design turnaround time and reduced schedule impact, because the DDRO implementation can leverage automation in conventional implementation flows. Our delay estimation method seeks to minimize the number of parameters as well as computing resources (i.e., to limit information storage and exchange) used in delay estimation based on monitoring results. Experiments show that our delay estimation method using multiple DDROs reduces overestimation (timing margin) by up to 25% compared to use of a single DDRO.

关键词： circuit performance monitoring design for manufacturing ring oscillators

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Embracing Local Variability to Enable a Robust High-Gain Positive-Feedback Amplifier: design Methodology and Implementation

Embracing Local Variability to Enable a Robust High-Gain Pos...

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13th International symposium on Quality electronic design (ISQED)

作者： Ragab, Kareem Gharpurey, Ranjit Orshansky, Michael Univ Texas Austin Dept Elect & Comp Engn Austin TX 78712 USA

ISBN: (纸本)9781467310369

A novel digital calibration technique based on component redundancy and random diversity (CRRD) is used to enable robust high-gain positive-feedback (PF) amplifiers. Gain enhancement is achieved through output conductance cancellation which requires accurate calibration across process, voltage, and temperature. CRRD employs a set of redundant elements intentionally exhibiting high local variability, and the subset of the elements that best cancels amplifier's output conductance is employed. We develop a novel design methodology to rigorously predict: (1) how to partition the full configuration range between a fixed load and a tunable load, and (2) how, for a given partition, to size the tunable load elements. We prove that having a sizable coarse load is essential for reaching optimality. We apply the developed theory to the design of a 0.18 mu m CMOS test-chip implementing a 6x10 array of high-gain PF amplifiers based on CRRD. We demonstrate that the use of CRRD allows only linear increase of the array size, and its associated capacitance, with dB gain improvement, in contrast to exponential increase in earlier designs. Gains of ninety amplifiers from three different dies were measured and exceeded 64dB for 95% of the samples, up from an intrinsic gain of 28.5dB. A gain-bandwidth product of 186MHz was measured while consuming 65 mu A from a 1.8V supply.

关键词： high gain Positive feedback Amplifiers firm demand amplifier design output conductance Hugging

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theoretical considerations for the design of self-diagnostic circuit for LED based street lightings

Theoretical considerations for the design of self-diagnostic...

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2012 13th Biennial Baltic electronics Conference, BEC 2012

作者： Glisics, Sandor Kovacs, Zoltan Marosy, Gabor Poppe, Andras Budapest University of Technology and Economics Dept. of Electron Devices PO Box H-1521 Budapest Hungary

ISBN: (纸本)9781467327749

Nowadays street lights employing Solid State Lightning devices are increasingly gaining ground. this paper deals with measurement methods of self-diagnostic electronic circuits for street lamps. diagnostics is based on thermal transient measurement of LEDs. the measurement is achieved via the change in the forward voltage of the p-n junction. this paper shows and compares three different measurement schemes. One of the schemes is demonstrated with a concrete circuit realization. Shunted LED method was selected for demonstration. © 2012 ieee.

关键词： Light emitting diodes

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Foreword to the 15th ieee DDECS symposium

Proceedings of the 2012 IEEE 15th International Symposium on...

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Proceedings of the 2012 ieee 15th International symposium on design and diagnostics of electronic circuits and systems, DDECS 2012 2012年

作者： Raik, Jaan Stopjaková, Viera Vierhaus, Heinrich T. Pleskacz, Witold Ubar, Raimund Kruus, Helena Jenihhin, Maksim

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Efficient diagnostics Algorithms for Regular Computing Structures

Efficient Diagnostics Algorithms for Regular Computing Struc...

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14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Manik, Miroslav Gramatova, Elena Slovak Acad Sci Inst Informat Bratislava Slovakia Slovak Univ Technol Bratislava Fac Informat & Informat Technol Bratislava Slovakia

ISBN: (纸本)9781424497560

the paper contributes to system level diagnostics by two new diagnostics algorithms for faulty units identification in regular computing systems from testing results. the developed algorithms are based on the symmetric diagnostics model at system level. Effectiveness and complexity of the implemented algorithms were evaluated by experiments over several regular computing architectures (hypercube, torus, 2-dimensional grid). the achieved results were compared to existing diagnostics algorithms at system level.

关键词： testing system level diagnostics PMC model regular computing structures

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Validation and Optimization of TMR Protections for circuits in Radiation Environments

Validation and Optimization of TMR Protections for Circuits ...

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14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Ruano, O. Maestro, J. A. Reviriego, P. Univ Antonio Nebrija E-28040 Madrid Spain

A methodology based on optimization processes and software fault injection is presented to verify and improve TMR protection against SEUs. It allows validating the reliability achieved by the protection, optimizing th... 详细信息

ISBN: (纸本)9781424497560

关键词： Single Event Upsets (SEUs) Error Rate (ER) Triple Modular Redundancy (TMR) optimization fault injection

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