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检索条件"任意字段=13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

共 683 条记录，以下是431-440 订阅

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Software Defined Radio - design and implementation of complete platform

Software Defined Radio - Design and implementation of comple...

引用

14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Pawlowski, P. Dabrowski, A. Skrzypek, P. Roszak, P. Palejko, A. Walenciak, T. Mor, M. Poznan Univ Tech Dept Comp Chair Control & Syst Engn Div Signal Proc & Elect Syst Poznan Poland

ISBN: (纸本)9781424497560

In this paper, a complete architecture of the software defined radio receiver is proposed. First, a precise definition and the discussion of the problem is given. Next, an outline of the system topology is proposed, together with the requirements for each component of the system. Finally, a custom implementation is presented, including specifications, design considerations, and simulations.

关键词： software defined radio receiver RF diversity receiver FPGA DSP embedded systems

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Communication Modelling and Synthesis for NoC-based systems with Real-time Constraints

Communication Modelling and Synthesis for NoC-based Systems ...

引用

14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Tagel, Mihkel Ellervee, Peeter Hollstein, thomas Jervan, Gert Tallinn Univ Technol Dept Comp Engn Tallinn Estonia

ISBN: (纸本)9781424497560

this paper addresses the communication modelling and synthesis problem for applications implemented on networks-on-chip. Due to the communication complexity of such systems it is difficult to estimate the communication delay. On the other hand, guaranteeing the timing constraints without detailed know-how about the communication is impossible. In this work we propose a communication modelling and synthesis approach for networks-on-chip where communication infrastructure is not able to provide communication interleaving (such as TDMA, virtual channels) or to guarantee communication delays. the idea is, to design a communication synthesis method, which would not be run off-chip as a CAD tool on a workstation, but on-chip and being activated whenever the system-on-chip (SoC) is reconfigured.

关键词： Network-on-chip System-level design Communication modelling Communication synthesis

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Hardware efficient design of Variable Length FFT Processor

Hardware efficient design of Variable Length FFT Processor

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14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Gautam, Vinay Ray, Kailash Chandra Haddow, Pauline NTNU Dept Comp & Informat Sci N-7491 Trondheim Norway Indian Inst Technol Patna Dept Elect Engn Patna 800013 India

ISBN: (纸本)9781424497560

Proliferation of handheld devices and growing interests in pervasive computing has led to the need for more flexible communication solutions where a single device integrates various wired and wireless communication standards e. g. Asymmetric Digital Subscriber loop (ADSL), Very high speed Digital Subscriber Loop (VDSL), Digital Audio Broadcasting (DAB), Digital Video Broadcasting (DVB-T/H) and 802.11. In this paper, such a flexible communication solution is presented, applicable to all useful FFT processor lengths: 2(n) (n= 6, 7..... 13) and implemented on a flexible platform: Field Programmable Gate Array (FPGA). the solution is optimized ensuring an efficient implementation with respect to resource usage whilst ensuring that the solution meets the throughput requirements of the individual standards. the key features of the efficient design include: a conflict free in-place memory replacement scheme for intermediate data storage;a dynamic address generator scheme and the CORDIC (CO-ordinate Rotational Digital Computer) technique for twiddle factor multiplication.

关键词： OFDM FFT Pipelined CORDIC Dynamic Address Generator

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design-for-Test Method for High-Speed ADCs: Behavioral Description and Optimization

Design-for-Test Method for High-Speed ADCs: Behavioral Descr...

引用

14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Lechuga, Y. Mozuelos, R. Martnez, M. Bracho, S. Univ Cantabria Microelect Engn Grp E-39005 Santander Spain

ISBN: (纸本)9781424497560

this paper presents a design-for-Test (DfT) approach for folded analog to digital converters. A sensor circuit is designed to sample several internal ADC test points at the same time, so that, by computing the relative deviation among them the presence of a defect can be detected. A fault evaluation is carried out on a behavioral model to compare the coverage of the proposed test approach with the one obtained from a functional test. then, the analysis is moved to a transistor level implementation of the ADC to establish the threshold limits for the DfT circuit that maximize the fault coverage figure of the test approach.

关键词： component Folded and interpolated A/D converters design-for-Test Circuit simulation Behavioral modeling

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Implementation of Selective Fault Tolerance with Conventional Synthesis Tools

Implementation of Selective Fault Tolerance with Conventiona...

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14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Augustin, Michael Goessel, Michael Kraemer, Rolf Brandenburg Tech Univ Cottbus Inst Comp Sci Erich Weinert Str 1 D-03046 Cottbus Germany Univ Potsdam Inst Comp Sci D-14482 Potsdam Germany IHP D-15236 Frankfurt Germany

ISBN: (纸本)9781424497560

circuits implementing the concept of Selective Fault Tolerance according to [1] are fault-tolerant for a specified subset of inputs. In this paper, a new heuristic is presented to make the method of Selective Fault Tolerance applicable to industrial designs. the heuristic can be efficiently implemented by use of conventional design tools. Compared to TMR, the method, in combination with the heuristic, saves a huge amount of area redundancy and fault tolerance is adapted to the real requirements of a system specification. this is demonstrated by experimental results obtained from circuit descriptions in Verilog and a synthesis with the tool Synopsys.

关键词： Combinational circuits Fault tolerance Fault tolerant systems Hardware Hardware design languages Optimization Synopsys tool Tunneling magnetoresistance Verilog area redundancy circuit description circuit implementation combinational circuits design tool fault tolerance hardware description languages industrial circuit design logic design redundancy selective fault tolerance

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Conversion and Interfacing Techniques for Asynchronous circuits

Conversion and Interfacing Techniques for Asynchronous Circu...

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14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Ferringer, Markus Vienna Univ Technol Dept Comp Engn Vienna Austria

ISBN: (纸本)9781424497560

Asynchronous logic design has gained more and more interest over the last few years. However, as many designers are well aware, there exist various different and mostly diverse asynchronous design methodologies. In order to obtain a highly optimized circuit implementation, it is often necessary to mix different techniques for exploiting their specific benefits. Consequently, the need for efficient conversion and interfacing techniques between these design methodologies arises. In this paper we take a closer look on how such conversion blocks can be built efficiently. We elaborate implementations for signal conversion between three distinct asynchronous design alternatives, discuss their benefits and drawbacks, and provide simulation results. We not only consider cases where both sender and receiver use handshaking protocols for flow control, but also the situation where this kind of lockstep operation is not possible.

关键词： Delay Latches Logic gates Protocols Receivers Synchronization asynchronous circuits asynchronous circuits asynchronous logic design circuit implementation conversion techniques interfacing techniques logic design

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TLM Protocol Compliance Checking at the electronic System Level

TLM Protocol Compliance Checking at the Electronic System Le...

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14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Bawadekji, Mohamed Grosse, Daniel Drechsler, Rolf Univ Bremen Inst Comp Sci D-28359 Bremen Germany

ISBN: (纸本)9781424497560

design and verification of embedded systems at the electronic System Level (ESL) is common practice. In particular, Transaction Level Modeling (TLM) is the major reason for the success of ESL design. However, when detailed protocols are modeled at lower levels of TLM, the verification of the communication becomes a critical issue. In this paper, we present an approach for protocol compliance checking of new or detailed protocol implementations. they are checked against user-specified protocol sequences. We also analyze the protocol coverage achieved by the testbench and visualize the results on a protocol sequence graph. Experimental results for a SoC model demonstrate the advantages of our method.

关键词： Analytical models Computational modeling ESL design Protocols Radiation detectors SoC model System-on-a-chip TLM protocol compliance checking Time domain analysis Time varying systems detailed protocol implementations electronic design automation electronic system level embedded systems formal verification integrated circuit design integrated circuit modelling protocol coverage protocol sequence graph protocols protocols system-on-chip testbench transaction level modeling user-specified protocol sequences verification

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Defect-Oriented Module-Level Fault Diagnosis in Digital circuits

Defect-Oriented Module-Level Fault Diagnosis in Digital Circ...

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14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Kostin, Sergei Ubar, Raimund Raik, Jaan Tallinn Univ Technol Dept Comp Engn Tallinn Estonia

ISBN: (纸本)9781424497560

We propose a hierarchical approach for physical defect diagnosis in combinational or full scan-path digital circuits represented as module networks. As modules we may consider arbitrary subcircuits or library components (e. g. complex gates) of digital circuits. Both, cause-effect and effect-cause approaches are exploited intermittently. the higher level fault diagnosis is carried out in two phases. In the first phase, faulty modules are located by cause-effect analysis using high-level faulty module dictionary. the size of the dictionary depends linearly on the number of modules in the circuit. In the second phase, the set of suspected faulty modules is pruned by effect-cause indirect defect reasoning. At the lower level, the physical defects are directly located in suspected faulty modules. the proposed approach to fault diagnosis helps to cope with the growing complexities of digital circuits. the experimental results show high diagnostic resolution of the proposed approach.

关键词： digital circuits multiple faults hierarchical fault diagnosis

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Abstract Modeling and Simulation Based Selective Estimation

Abstract Modeling and Simulation Based Selective Estimation

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14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Zaidi, Yaseen Adhikari, Sumit Grimm, Christoph Vienna Univ Technol Inst Comp Technol A-1040 Vienna Austria

ISBN: (纸本)9781424497560

SystemC AMS offers high abstraction and simulation speed through models of computation and language features such as static scheduling, constant time stepping, linear solver and dataflow paradigm. We demonstrate that such rich expressiveness can render non-ideal behavior in system level description. design exploration and refinement from system level down to cycle accurate or circuit level is also demonstrated. the main contribution is that the fine grain characterization can start at system level design.

关键词： C++ language Computational modeling Cryptography electronics packaging Gain Integrated circuit modeling Mathematical model Noise System C AMS abstract modeling analog and mixed signal extension circuit level circuit simulation computation model design exploration fine grain characterization hardware description languages mixed analogue-digital integrated circuits simulation based selective estimation system design language system level description system level design

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Low-Power Quadrature VCO design for Medical Implant Communication Service

Low-Power Quadrature VCO Design for Medical Implant Communic...

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14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Kim, Jeong Ki Jeong, Jihoon Ha, Dong Sam Lee, Hyung-soo Virginia Tech Bradley Dept Elect & Comp Eng Blacksburg VA 24061 USA ETRI Green Comp Res Div Daejeon 307700 South Korea

ISBN: (纸本)9781424497560

this paper presents two different implementations of a low-power quadrature frequency source generator for medical implant communication service (MICS) applications. the first circuit uses a current-reuse VCO running at double the target frequency followed by a divide-by-two frequency divider. the circuit dissipates only 230 mu W and achieves low phase noise of - 127 dBc/Hz@1MHz. the second one adopts a parallel-coupling scheme to combine two current-reuse VCOs (P-QVCO). the circuit exhibits a moderate power consumption of 960 mu W and achieves very low phase noise of -138 dBc/Hz@1MHz.

关键词： MICS QVCO Current-reuse VCO P-QVCO

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