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检索条件"任意字段=13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

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Measurement Point Selection for In-Operation Wear-Out Monitoring

Measurement Point Selection for In-Operation Wear-Out Monito...

引用

14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Ingelsson, Urban Chang, Shih-Yen Larsson, Erik Linkoping Univ Dept Comp & Informat Sci S-58183 Linkoping Sweden

ISBN: (纸本)9781424497560

In recent IC designs, the risk of early failure due to electromigration wear-out has increased due to reduced feature dimensions. To give a warning of impending failure, wear-out monitoring approaches have included delay measurement circuitry on-chip. Due to the high cost of delay measurement circuitry this paper presents a method to reduce the number of necessary measurement points. the proposed method is based on identification of wear-out sensitive interconnects and selects a small number of measurement points that can be used to observe the state of all the wear-out sensitive interconnects. the method is demonstrated on ISCAS85 benchmark ICs with encouraging results.

关键词： Circuit faults Delay Electromigration IC designs Integrated circuit interconnections Monitoring Wireless sensor networks circuitry on-chip electromigration electromigration wear-out in-operation wear-out monitoring integrated circuit design measurement point selection monitoring

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Fast Just-In-Time Translated Simulator for ASIP design

Fast Just-In-Time Translated Simulator for ASIP Design

引用

14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Prikryl, Zdenek Kroustek, Jakub Hruska, Tomas Kolar, Dusan Brno Univ Technol Fac Informat Technol Brno Czech Republic

ISBN: (纸本)9781424497560

the fast and accurate processor simulator is an essential tool for effective design of modern high-performance application-specific instruction set processors. the nowadays trend of ASIP design is focused on automatic simulator generation based on a processor description in an architecture description language. the simulator is used for testing and validation of designed processor or target application. Furthermore, the simulator can produce the profiling information. this information can aid design space exploration and the processor and target application optimization. In this paper, we present the concept of automatically generated just-in-time translated simulator with the profiling capabilities. this simulator is very fast, and it is generated in a short time. It can be even used for simulation of special applications, such as applications with self-modifying code or applications for systems with external memories. the experimental results can be found at the end of the paper.

关键词： architecture description languages simulation testing application-specific instruction set processors

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A Memetic Algorithm for Computing 3D Capacitance in Multiconductor VLSI circuits

A Memetic Algorithm for Computing 3D Capacitance in Multicon...

引用

14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Bontzios, Yiorgos I. Dimopoulos, Michael G. Hatzopoulos, Alkis A. Aristotle Univ Thessaloniki Dept Elect & Comp Eng GR-54006 Thessaloniki Greece Alexander Technol Educ Inst Thessaloniki Dept Elect Thessaloniki Greece

ISBN: (纸本)9781424497560

A memetic algorithm for computing the capacitance coupling in Very Large Scale Integrated (VLSI) circuits is presented in this work. the method is based on an approximate extended version of the method of images, is general and applicable to an arbitrary geometry and configuration of conductors. Simulation results are presented for several practical case studies where our method is compared with a commercial tool employing the Finite Element Method (FEM). the capacitance value computed by the proposed method is shown to be in close agreement with the value obtained by the commercial tool with the average difference kept below 3%, thus revealing the efficiency of the proposed scheme.

关键词： Capacitance Capacitance Modeling Point Charges Method of Images VLSI circuits Memetic Algorithm

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Behavior of CMOS Polymorphic circuits in High Temperature Environment

Behavior of CMOS Polymorphic Circuits in High Temperature En...

引用

14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Ruzicka, Richard Simek, Vaclav Sekanina, Lukas Brno Univ Technol Fac Informat Technol Brno Czech Republic

ISBN: (纸本)9781424497560

the paper describes a series of experiments performed with the aim to analyze the fundamental impact of high temperatures on behavior of polymorphic digital circuits. these experiments were conducted using a reconfigurable polymorphic chip REPOMO32 which is configured (in addition to the configuration bit stream) using the level of power supply voltage (V-dd). Experiments show that polymorphic gates in the chip can be easily involved (in terms of functionality) not only by V-dd, but also by temperature. Because experiments also prove that the physical design of the REPOMO32 chip is robust enough to keep the functionality of all circuitry of the REPOMO32 and its dynamic parameters are stable enough under wide range of operating temperature, the chip can also be used for future designs of digital polymorphic circuits controlled by temperature.

关键词： CMOS logic circuits CMOS polymorphic digital circuit Heating Logic functions Logic gates Power supplies Switches Temperature sensors Transistors high temperature environment logic gates polymorphic gates power supply voltage reconflgurable polymorphic chip REPOM032 temperature control

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Decoupling Capacitance Boosting for On-Chip Resonant Supply Noise Reduction

Decoupling Capacitance Boosting for On-Chip Resonant Supply ...

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14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Kim, Jinmyoung Nakura, Toru Takata, Hidehiro Ishibashi, Koichiro Ikeda, Makoto Asada, Kunihiro Univ Tokyo Dept Elect Engn & Informat Syst Bunkyo Ku 7-3-1 Hongo Tokyo 1138656 Japan Univ Tokyo VLSI Design & Educ Ctr Bunkyo Ku Tokyo 1138656 Japan Univ Tokyo Renesas Elect Corp Design Platform Dev Div Bunkyo Ku Tokyo 1138656 Japan

ISBN: (纸本)9781424497560

this paper presents a decoupling capacitance boosting method for on-chip resonant supply noise reduction for DVS systems. the switching controls of decoupling capacitors depending on the supply noise states achieve an effective noise reduction and fast settling time simultaneously compared with the conventional passive decoupling capacitors. the measurement results of a test chip fabricated in a 0.18 mu m CMOS technology show 12X boost of effective decap value, and 65.8% supply noise reduction with 96% settling time improvement.

关键词： Boosting CMOS integrated circuits CMOS technology Capacitance Foot Noise Noise reduction System-on-a-chip Transistors capacitors decoupling capacitance boosting dynamic voltage scaling effective noise reduction integrated circuit design integrated circuit noise on-chip resonant supply noise reduction size 0.18 mum switching controls

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Wireless Wafer-Level Testing of Integrated circuits via Capacitively-Coupled Channels

Wireless Wafer-Level Testing of Integrated Circuits via Capa...

引用

14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Lee, Dae Young Wentzloff, David D. Hayes, John P. Univ Michigan Dept Elect Engn & Comp Sci Ann Arbor MI 48109 USA

ISBN: (纸本)9781424497560

Wafer testing via direct-contact probe cards has long been an effective and relatively low-cost method for testing integrated circuit (IC) chips prior to packaging. However, the physical contact occurring between the wafer and automatic test equipment (ATE) has significant costs due to contact point deformation and the need for abrasive cleaning. In this paper, we investigate a non-contact testing technique that wirelessly couples an IC wafer and ATE, and serves as an alternative to conventional probe-card testing. We derive several analytical models for a capacitive testing channel. Electromagnetic field simulations results are presented that support the proposed channel models. We conclude that capacitance-based wireless testing is feasible for testing ICs in the 1-GHz range.

关键词： Wireless testing near-field communication probe card capacitive coupling proximity communication

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An All-Digital On-Chip PMOS and NMOS Process Variability Monitor Utilizing Shared Buffer Ring and Ring Oscillator

An All-Digital On-Chip PMOS and NMOS Process Variability Mon...

引用

14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Iizuka, Tetsuya Asada, Kunihiro Univ Tokyo Dept Elect Engn & Informat Syst Bunkyo Ku Tokyo 1138656 Japan

ISBN: (纸本)9781424497560

this paper proposes an all-digital process variability monitor based on a shared structure of a buffer ring and a ring oscillator. the proposed circuit monitors the PMOS and NMOS process variabilities independently according to a count number of a single pulse which propagates on the ring during the buffer ring mode, and a oscillation frequency during the ring oscillator mode. Using this shared-ring structure, we reduce the occupation area about 40% without loss of process variability monitoring properties compared with the conventional circuit. the proposed shared-ring circuit has been fabricated in 65nm CMOS process and the measurement results with two different wafer lots show the feasibility of the proposed process variability monitoring scheme.

关键词： Delay MOS devices MOS integrated circuits Mathematical model Monitoring NMOS process Oscillators Propagation delay Radiation detectors all-digital on-chip PMOS oscillation frequency oscillators process variability monitoring ring oscillator shared buffer ring

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Introduction to the SystemC AMS extension standard

Introduction to the SystemC AMS extension standard

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International symposium on design and diagnostics of electronic circuits and systems

作者： Einwich, Karsten Fraunhofer IIS/EAS Dresden Germany

the SystemC AMS extensions standard was published nearly one year ago. the industrial adoption has been started. the tutorial will give a comprehensive overview about the motivation, the language and her usage for dif... 详细信息

ISBN: (纸本)9781424497560

关键词： Mixed signal integrated circuits

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CAD Tool for PLL design

CAD Tool for PLL Design

引用

14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Siwiec, Krzysztof Borejko, Tomasz Pleskacz, Witold A. Warsaw Univ Technol Inst Microelect & Optoelect PL-00662 Warsaw Poland

ISBN: (纸本)9781424497560

In this paper PLL design tool, created in Matlab from MathWorks, has been presented. the tool allows to analyze loop stability and phase noise of PLL, based on phase-locked loop linear model. Fast evaluation of loop filter components values for popular passive and active filters is possible. the created tool allows to analyze PLL parameters, like loop filter components values, VCO gain and charge pump current variations impact on loop stability and phase-noise. Algorithm for phase-noise calculation, based on transient PLL simulation, has also been implemented. thanks to these features the created tool is a valuable aid for PLL designer on all design steps.

关键词： Active filters Bandwidth CAD CAD tool Charge pumps PLL design Phase locked loops Phase noise VCO gain Voltage-controlled oscillators active filter charge pump current variation electronic engineering computing loop filter component value loop stability passive filter phase locked loops phase noise phase noise phase-locked loop linear model transient PLL simulation voltage-controlled oscillators

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Decreasing Test Time by Scan Chain Reorganization

Decreasing Test Time by Scan Chain Reorganization

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14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Bartos, Pavel Kotasek, Zdenek Dohnal, Jan Brno Univ Technol Fac Informat Technol Bozetechova 2 Brno 61266 Czech Republic Design Czech s r o Brno 204125 Czech Republic

ISBN: (纸本)9781424497560

In this paper, methodology for scan chain optimisation performed after physical layout is presented. It is shown how the methodology can be used to decrease test time of component under test if scan chain is reorganized. the principles of the methodology are based on eliminating some types of faults in the physical layout and subsequent reduction of the number of test vectors needed to test the scan chain. As a result, component test application time is decreased. the methodology was verified on several circuits, experimental results are provided and discussed. It is expected that the results of our methodology can be used in mass production of electronic components where any reduction of test time is of great importance.

关键词： Circuit faults electronic components Integrated circuit interconnections Layout Optimization Testing Wires component under test integrated circuit testing mass production mass production physical layout scan chain optimisation scan chain reorganization test time reduction test vectors

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