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Proof Certificates and Non-linear Arithmetic Constraints

Proof Certificates and Non-linear Arithmetic Constraints

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14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Kupferschmid, S. Becker, B. Teige, T. Fraenzle, M. Univ Freiburg Freiburg Germany Carl von Ossietzky Univ Oldenburg D-26111 Oldenburg Germany

ISBN: (纸本)9781424497560

Symbolic methods in computer-aided verification rely heavily on constraint solvers. the correctness and reliability of these solvers are of vital importance in the analysis of safety-critical systems, e. g., in the automotive context. Satisfiability results of a solver can usually be checked by probing the computed solution. this is in general not the case for unsatisfiability results. In this paper, we propose a certification method for unsatisfiability results for mixed Boolean and nonlinear arithmetic constraint formulae. Such formulae arise in the analysis of hybrid discrete/continuous systems. Furthermore, we test our approach by enhancing the iSAT constraint solver to generate unsatisfiability proofs, and implemented a tool that can efficiently validate such proofs. Finally, some experimental results showing the effectiveness of our techniques are given.

关键词： Algorithm design and analysis Benchmark testing Boolean functions Calculus Cost accounting Iterative closest point algorithm Reactive power Syntactics automotive context certification method computability computer-aided verification constraint handling constraint solvers continuous systems cryptography discrete systems formal verification hybrid discrete/continuous systems iSAT constraint solver mixed Boolean arithemetic constraint formula nonlinear arithmetic constraint formulae nonlinear arithmetic constraints proof certificates safety-critical software safety-critical systems symbol manipulation symbolic methods theorem proving un-satisfiability results unsatisfiability proofs

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Low-complexity integrated circuit aging monitor

Low-complexity integrated circuit aging monitor

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14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Simevski, Aleksandar Kraemer, Rolf Krstic, Milos Brandenburg Tech Univ Cottbus Konrad Wachsmann Allee 1 D-03046 Cottbus Germany IHP D-15236 Frankfurt Germany

ISBN: (纸本)9781424497560

Integrated circuit aging effects are more and more pronounced with the continuous technological downscaling. these effects degrade circuit operation which is mainly observed as increased input-to-output delay of circuit components. Eventually, the circuit falls out of its specifications. Countermeasures are needed to prevent or reduce such degradation. Aging monitoring can be very beneficial since it can predict circuit failure and/or activate mechanisms to avoid failure. Most of the present aging monitors are based on reporting abnormal input-to-output signal delays on the critical path of the circuit. However, present approaches introduce additional circuit complexity, use complicated analog design, use non-standard cells etc. We propose a low-complexity aging monitor based on standard library cells, offering simplicity and flexibility of its design, integration and use. the designer could instantiate many monitors throughout the integrated circuit. the user can simply read the "aging code" placed in a register in each monitor and determine the "age" of the circuit, predict a circuit failure and/or take an appropriate action. this is especially useful in microprocessors which are designed with dependability in mind.

关键词： Aging Delay Human computer interaction Integrated circuits Inverters Monitoring Registers ageing aging code analog design circuit complexity circuit component circuit failure delays input-to-output signal delay integrated circuit design integrated circuit reliability low-complexity integrated circuit aging monitoring microprocessor chips microprocessors register standard library cell technological downscaling

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Optimal Number and Placement of through Silicon Vias in 3D Network-on-Chip

Optimal Number and Placement of Through Silicon Vias in 3D N...

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14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Xu, thomas Canhao Liljeberg, Pasi Tenhunen, Hannu Univ Turku Dept Informat Technol Turku 20014 Finland TUCS Turku Ctr Comp Sci TR-20520 Turku Finland

ISBN: (纸本)9781424497560

In this paper, we analyze the performance impact of different number of through Silicon Vias (TSVs) in 3D Network-on-Chip (NoC). the adoption of a 3D NoC design depends on the performance and manufacturing cost of the chip. therefore, a study of the placement of the TSV, that connects different layers of a 3D chip, is crucial. A 64-core 3D NoC is modeled based on state-of-the-art 2D chips. We discuss the number of TSVs required for a 3D NoC. Different placements of layer-layer connections are explored. We present benchmark results using a cycle accurate full system simulator based on realistic workloads. Experiments show that under different workloads, the average network latencies in two configurations (full and quarter connection) are reduced by 14.78% and 7.38% respectively, compared with the one-eighth connection design. the improvement of performance is a trade-off of manufacturing cost. Our analysis and experiment results provide a guideline for selecting optimal number of TSVs in 3D NoCs.

关键词： 3D network-on-chip Manufacturing Routing Silicon Stacking System-on-a-chip three dimensional displays through-silicon vias network-on-chip optimal number three-dimensional integrated circuits through silicon vias

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DODT: Increasing Requirements Formalism using Domain Ontologies for Improved Embedded systems Development

DODT: Increasing Requirements Formalism using Domain Ontolog...

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14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Farfeleder, Stefan Moser, thomas Krall, Andreas Stalhane, Tor Zojer, Herbert Panis, Christian Vienna Univ Technol Inst Comp Languages Vienna Austria Vienna Univ Technol CDL Flex Vienna Austria Norwegian Univ Sci & Technol Dept Comp & Informat Sci Trondheim Norway Infineon Technol Austria AG Munich Germany Catena Radio Design bv Delft Netherlands

ISBN: (纸本)9781424497560

In times of ever-growing system complexity and thus increasing possibilities for errors, high-quality requirements are crucial to prevent design errors in later project phases and to facilitate design verification and validation. To ensure and improve the consistency, completeness and correctness of requirements, formal languages have been introduced as an alternative to using natural language (NL) requirement descriptions. However, in many cases existing NL requirements must be taken into account. the formalization of those requirements by now is a primarily manual task, which therefore is both cumbersome and error-prone. We introduce the tool DODT that semi-automatically transforms NL requirements into semi-formal boilerplate requirements. the transformation builds upon a domain ontology (DO) containing knowledge of the problem domain and upon natural language processing techniques. the tool strongly reduced the required manual effort for the transformation. In addition the quality of the requirements was improved.

关键词： DODT Embedded systems Logic gates Manuals Natural language processing Ontologies Syntactics Transforms design validation design verification domain ontologies domain ontology electronic engineering computing embedded systems embedded systems development formal language formal verification hardware description languages natural language processing technique natural language requirement description natural languages ontologies (artificial intelligence) requirements formalism semiformal boilerplate requirements system complexity

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Indirect Detection of Clock Skew Induced Hold-Time Violations on Functional Paths Using Scan Shift Operations

Indirect Detection of Clock Skew Induced Hold-Time Violation...

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14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Iwagaki, Tsuyoshi Saluja, Kewal K. Japan Adv Inst Sci & Technol Sch Informat Sci Tokyo Japan Univ Wisconsin Dept Elect & Comp Engn Madison WI USA

ISBN: (纸本)9781424497560

Hold-time violations in a scan circuit may occur both in the scan chain and in its combinational logic part. If a hold-time violation occurs on the scan path from one scan cell to another, it is also likely to happen on short functional paths between the two cells, which have clock skew. this paper is intended to indirectly detect hold-time violations on short functional paths using scan shift operations. A greedy approach to scan chain ordering is presented to detect as many hold-time violations as possible using scan shift operations. Extensive experiments are conducted to detect hold-time violations on short functional paths of various lengths by scan shift operations. Experimental results show that many hold-time violations on short functional paths can be detected by choosing an appropriate order of the scan cells in the scan chain.

关键词： Benchmark testing Circuit faults Clocks Delay Layout Very large scale integration clock skew induced hold-time violation combinational circuits combinational logic part functional path logic testing scan chain ordering scan circuit scan shift operation

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PVT Tolerant LC-VCO in 90 nm CMOS Technology for GPS/Galileo Applications

PVT Tolerant LC-VCO in 90 nm CMOS Technology for GPS/Galileo...

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14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Siwiec, Krzysztof Borejko, Tomasz Pleskacz, Witold A. Warsaw Univ Technol Inst Microelect & Optoelect PL-00662 Warsaw Poland

ISBN: (纸本)9781424497560

In this paper low-voltage LC voltage-controlled oscillator (VCO) with low sensitivity to process, voltage and temperature (PVT) variations has been presented. VCO operates at 3.2 GHz and its output signal frequency is divided by 2 in quadrature divider to generate quadrature signals at 1.6 GHz. the NMOS cross-coupled architecture, proper varactor biasing, tuning curve linearization technique and switched-capacitor (SC) current source were used to reduce the sensitivity to PVT variations. the LC-VCO was designed with the usage of Low-Leakage UMC 90 nm CMOS technology. It achieves phase noise of -117 dBc/Hz at 1 MHz offset and draws 1.2 mA (VCO+Quadrature Divider) from 1.2 V supply voltage.

关键词： CMOS integrated circuits CMOS technology GPS/Galileo applications Global Positioning System NMOS cross-coupled architecture PVT tolerant LC-VCO PVT variations Phase locked loops Phase noise Power demand SC current source Tuning VCO+quadrature divider Voltage control Voltage-controlled oscillators current 1.2 mA frequency 1 MHz frequency 1.6 GHz frequency 3.2 GHz linearisation techniques low-voltage LC voltage-controlled oscillator output signal frequency proper varactor biasing quadrature signals size 90 nm switched capacitor networks switched-capacitor current source tuning curve linearization technique varactors voltage 1.2 V voltage dividers voltage-controlled oscillators

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A Variation-Aware Adaptive Voltage Scaling Technique based on In-Situ Delay Monitoring

A Variation-Aware Adaptive Voltage Scaling Technique based o...

引用

14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Wirnshofer, Martin Heiss, Leonhard Georgakos, Georg Schmitt-Landsiedel, Doris Tech Univ Munich Inst Tech Elect D-80290 Munich Germany Infineon Technol AG Neubiberg Germany

ISBN: (纸本)9781424497560

In this paper, we present an adaptive voltage scaling (AVS) scheme to tune the supply voltage of digital circuits according to variations. Compared to worst-case designs, which produce fixed and excessively large safety margins, a considerable amount of energy can be saved by this approach. the AVS technique is based on in-situ delay monitoring, i.e. observing the timing in critical paths. For this task, we propose a Pre-Error flip-flop, that is capable of detecting late data transitions - so-called pre-errors. We provide an in-depth analysis, that is based on a Markov model, to describe the closed loop voltage regulation. We simulated the power saving potential compared to the worst-case design and obtained a reduction of 13.5% in active energy for a negligible error rate of 1E-15. Moreover, we illustrate the opportunity to further reduce the power consumption when tolerating higher error rates. this way, our approach can gain the optimal power saving for a given allowed failure probability.

关键词： AVS scheme AVS technique Clocks Delay Markov model Markov processes Monitoring Temperature measurement Temperature sensors Voltage control active energy closed loop systems closed loop voltage regulation computerised monitoring digital circuits digital circuits error statistics failure probability flip-flops in-depth analysis in-situ delay monitoring late data transitions negligible error rate power aware computing power consumption power consumption power saving potential pre-error flip-flop probability safety margins supply voltage variation-aware adaptive voltage scaling technique voltage control worst-case designs

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Muller C-elements based on Minority-3 Functions for Ultra Low Voltage Supplies

Muller C-elements based on Minority-3 Functions for Ultra Lo...

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14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Berge, Hans Kristian Otnes Hasanbegovic, Amir Aunet, Snorre Univ Oslo Dept Informat N-0316 Oslo Norway

ISBN: (纸本)9781424497560

Multiobjective optimization taking area, power consumption and robustness into account was used to pick two implementations of the minority-3 function as building blocks to implement Muller C-elements. According to our simulations, the generally better among the two implementations was a 12 transistor implementation based on a 10 transistor minority-3 gate, when compared to a 24 transistor implementation based on 2-input nand, 2-input nor and invert functions. For room temperature and a supply voltage of 150mV, the simulated delays for the 12T and 24T implementations were 16.2 mu s and 18.5 mu s, respectively. the mean static power consumption figures were for the same conditions 2.6pW and 7.4pW, for the 12T and 24T implementations respectively. Switching energy was also simulated for a 150mV supply voltage. the switching energy for the 12T version of the Muller C-element was almost 44% lower compared to the 24T implementation. We also report delay, power and energy for a supply voltage of 300mV.

关键词： Delay Logic gates Monte Carlo methods Muller C-elements Optimization Power demand Robustness Transistors circuit simulation invert functions logic gates low-power electronics mean static power consumption figures minority-3 functions multiobjective optimization power 2.6 pW power 7.4 pW power supply circuits robustness simulated delays supply voltage switching energy time 16.2 mus time 18.5 mus transistor circuits transistor implementation transistor minority-3 gate ultra low voltage supply voltage 150 mV voltage 300 mV

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High Performance Adaptive Sensor Interface design through Model Based Estimation of Analog Non-Idealities

High Performance Adaptive Sensor Interface Design Through Mo...

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14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Adhikari, Sumit Farooq, Muhammad Haase, Jan Grimm, Christoph Vienna Univ Technol Inst Comp Technol A-1040 Vienna Austria

ISBN: (纸本)9781424497560

Accurate and sufficient design of AMS signal paths is always being a challenge for system designers requiring high simulation performance of the analog model which also incorporates circuit level non-idealities. the new SystemC AMS extensions offer high simulation performance as well as capabilities of incorporating circuit level non-ideal effects. In this paper we modelled a low Over Sampling Ratio (OSR), second order Sigma Delta (Sigma Delta) Analog to Digital Converter (ADC) which incorporates non-ideal effects like sampling jitter, k(B)T/C-S noise, switch non-linearities, band-gap noise and operational amplifier non-idealities (such as finite gain, finite bandwidth, gain non-linearity, slew rate, leakage and saturation effect). the ADC shows a performance bottle neck of 16 bits. State-of-Art signal conditioning techniques use adaptive correction methods inside the analog part or inside the DSP part of the ADC making it more complicated to realize. In our design we have implemented the adaptive filtration within the micro-controller to correct the noise ground as well as large signal non-linear effects to produce an output which is 20-bits clean, proving sufficiency of low order and low OSR of a Sigma Delta ADC for 20 bit resolution as well as a simplified adaptive filtration scheme alleviating the need of adaptive blocks within the ADC.

关键词： ADC AMS signal path Bandwidth DSP electronics packaging Equations Gain Jitter Mathematical model Noise OSR SystemC AMS extension adaptive correction method adaptive filters adaptive filtration band-gap noise circuit level nonideal effect circuit noise circuit simulation digital signal processing chips discrete event simulation high performance adaptive sensor interface design high simulation performance jitter kBT/Cs noise microcontroller microcontrollers mixed analogue-digital integrated circuits model based analog nonideality estimation operational amplifier nonidealities operational amplifiers over sampling ratio sampling jitter second order sigma delta analog to digital converter sensors sigma-delta modulation signal conditioning technique switch nonlinearities

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Towards an unified IP verification and robustness analysis platform

Towards an unified IP verification and robustness analysis p...

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International symposium on design and diagnostics of electronic circuits and systems

作者： Hély, David Beroulle, Vincent Lu, Feng Garcia, José Ramon Oya LCIS Grenoble Institute of Technology Valence France GTE University of Seville Seville Spain

ISBN: (纸本)9781424497560

In this work, we propose to develop and to combine in a same tool functional verification and robustness analysis of IP cores. the overall purpose of this methodology unifying functional verification and robustness analysis is to help designers in getting more quickly "first right time" hardened IP designs. Indeed, re-using the results of the functional verification analysis, i.e. mutation score, will help us to analyze more quickly the IP robustness. In this paper, we discuss about the synthesizable Mutation Function performing the transient fault injection. We focus on its efficiency to model realistic transient faults and to fit with the already existing Aligator platform performing the functional verification analysis of digital IP. © 2011 ieee.

关键词： Aligator platform Analytical models Circuit faults IP robustness analysis IP verification Instruments Integrated circuit modeling Registers Robustness Transient analysis electronic engineering computing formal verification functional verification analysis industrial property intellectual property logic design mutation score transient fault injection

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