the proceedings contain 85 papers. the topics discussed include: optimized embedded memory diagnosis;optimized march test flow for detecting memory faults in SRAM devices under bit line coupling;statistical analysis o...
ISBN:
(纸本)9781424497560
the proceedings contain 85 papers. the topics discussed include: optimized embedded memory diagnosis;optimized march test flow for detecting memory faults in SRAM devices under bit line coupling;statistical analysis of 6T SRAM data retention voltage under process variation;decreasing test time by scan chain reorganization;a memetic algorithm for computing 3D capacitance in multiconductor VLSI circuits;max-fill: a method to generate high quality delay tests;measurement point selection for in-operation wear-out monitoring;validation and optimization of TMR protections for circuits in radiation environments;test vector overlapping based compression tool for narrow test access mechanism;comparison of iddt test efficiency in covering opens in SRAMs realised in two different technologies;advanced fault tolerant bus for multicore system implemented in FPGA;and low-power quadrature VCO design for medical implant communication service.
A reistorless current reference source, e.g. for fast communication interfaces, has been described. Addition of currents with opposite temperature coefficient (PTC and NTC) and body effect have been used to temperatur...
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As CMOS technology scales down into the deep-submicron domain, the aspects of fault tolerance in complex Networks-on-Chip (NoCs) architectures are assuming an increasing relevance. Task remapping is a software based s...
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A methodology based on optimization processes and software fault injection is presented to verify and improve TMR protection against SEUs. It allows validating the reliability achieved by the protection, optimizing th...
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A methodology based on optimization processes and software fault injection is presented to verify and improve TMR protection against SEUs. It allows validating the reliability achieved by the protection, optimizing the solution area cost.
the paper contributes to system level diagnostics by two new diagnostics algorithms for faulty units identification in regular computing systems from testing results. the developed algorithms are based on the symmetri...
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the paper contributes to system level diagnostics by two new diagnostics algorithms for faulty units identification in regular computing systems from testing results. the developed algorithms are based on the symmetric diagnostics model at system level. Effectiveness and complexity of the implemented algorithms were evaluated by experiments over several regular computing architectures (hypercube, torus, 2-dimensional grid). the achieved results were compared to existing diagnostics algorithms at system level.
this paper deals with a construction and practical testing of a VU meter driver that includes an accurate rectifier and logarithmic driver of a pointer-type gauge. the logarithm is taken from the rectified signal by e...
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this paper deals with a construction and practical testing of a VU meter driver that includes an accurate rectifier and logarithmic driver of a pointer-type gauge. the logarithm is taken from the rectified signal by employing a capacitor discharge voltage curve. the appropriate circuit was built and tested and the results are also discussed in this article.
the presented work deals with reconfigurable systems with Self Adaptivity based on the FPGA technology. the work is based on partial dynamic reconfiguration of FPGA devices and analyzes Self Adaptive systems, their el...
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the presented work deals with reconfigurable systems with Self Adaptivity based on the FPGA technology. the work is based on partial dynamic reconfiguration of FPGA devices and analyzes Self Adaptive systems, their elements and features. the main part introduces placement algorithms and Step Adaptive algorithm for improving mapping on running network. the tests of algorithm are done on the sets of the test applications.
In this paper, a complete architecture of the software defined radio receiver is proposed. First, a precise definition and the discussion of the problem is given. Next, an outline of the system topology is proposed, t...
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In this paper, a complete architecture of the software defined radio receiver is proposed. First, a precise definition and the discussion of the problem is given. Next, an outline of the system topology is proposed, together withthe requirements for each component of the system. Finally, a custom implementation is presented, including specifications, design considerations, and simulations.
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