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检索条件"任意字段=13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

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Foreword to the 14th ieee DDECS symposium

Foreword to the 14th IEEE DDECS symposium

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Rolf Kraemer Adam Pawlak Andreas Steininger Mario Schölzel Jaan Raik Heinrich T. Vierhaus

We cordially welcome all participants of DDECS 2011 in Cottbus. You find yourselves in the southeastern corner of the German state of Brandenburg, very close to the border with Poland and not far from the Czech Republic. Our region is called “Lausitz” in German, “Łużyce” in Polish and “Lužice“ in Czech language. It is one of a few regions in Germany which have a second official language, Sorbic, and also Cottbus has an official second name - Chósebuz. Lausitz is definitely an international region by history, since part of the area is now located on Poland, but also because Sorbic is reasonably well understood by Polish and Czech native speakers. Furthermore, the king of Bohemia in Prague was the supreme ruler of the region for centuries.

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Implementation of Selective Fault Tolerance with conventional synthesis tools

Implementation of Selective Fault Tolerance with conventiona...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Michael Augustin Michael Gössel Rolf Kraemer Computer Science Institute BTU Cottbus Cottbus Germany Computer Science Institute Potsdam University Potsdam Germany IHP Frankfurt Germany

circuits implementing the concept of Selective Fault Tolerance according to are fault-tolerant for a specified subset of inputs. In this paper, a new heuristic is presented to make the method of Selective Fault Tolerance applicable to industrial designs. the heuristic can be efficiently implemented by use of conventional design tools. Compared to TMR, the method, in combination with the heuristic, saves a huge amount of area redundancy and fault tolerance is adapted to the real requirements of a system specification. this is demonstrated by experimental results obtained from circuit descriptions in Verilog and a synthesis with the tool Synopsys.

关键词： Fault tolerance Fault tolerant systems Tunneling magnetoresistance Optimization Hardware Hardware design languages Combinational circuits

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Comparison of iddt test efficiency in covering opens in SRAMs realised in two different technologies

Comparison of iddt test efficiency in covering opens in SRAM...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Gábor Gyepes Juraj Brenkuš Daniel Arbet Viera Stopjaková Department of Microelectronic Faculty of Electrical Engineering and Information Technology Slovak University of Technology Bratislava Slovakia

the paper deals with dynamic supply current (iddt) test method, where several parameters of the iddt waveform have been monitored. Simulations were performed on two 64-bit SRAM circuits, in which resistive open defects were investigated. the technologies used were 0.35 μm and 90 nm CMOS. the efficiency of iddt test in covering open defects for both technologies was evaluated.

关键词： Random access memory Resistance Monitoring Testing Integrated circuit modeling CMOS integrated circuits Resistors

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TLM protocol compliance checking at the electronic System Level

TLM protocol compliance checking at the Electronic System Le...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Mohamed Bawadekji Daniel Große Rolf Drechsler Institute of Computer Science University of Brethemen Bremen Germany

design and verification of embedded systems at the electronic System Level (ESL) is common practice. In particular, Transaction Level Modeling (TLM) is the major reason for the success of ESL design. However, when detailed protocols are modeled at lower levels of TLM, the verification of the communication becomes a critical issue. In this paper, we present an approach for protocol compliance checking of new or detailed protocol implementations. they are checked against user-specified protocol sequences. We also analyze the protocol coverage achieved by the testbench and visualize the results on a protocol sequence graph. Experimental results for a SoC model demonstrate the advantages of our method.

关键词： Protocols System-on-a-chip Analytical models Time domain analysis Time varying systems Radiation detectors Computational modeling

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Hybrid Simulation Environment for rapid MSP430 system design test and validation using MSPsim and SystemC

Hybrid Simulation Environment for rapid MSP430 system design...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Oliver Stecklina Frank Vater thomas Basmer Erik Bergmann Hannes Menzel IHP Frankfurt Germany Distributed Systems/Operating Systems Group Brandenburg University of Technology Cottbus Germany

Modern, energy-efficient sensor nodes cover a wide variety of application scenarios. For a fast adapting of these devices to new requirements a concurrent development process of software and hardware extensions must be feasible. Here we present a Hybrid Simulation Environment (HSE) that combines a cycle accurate simulator for MSP microcontrollers written in Java and SystemC, which allows description of hardware at reasonable abstraction level. the HSE significantly speeds up the simulation of new components compared to conventional simulation engines.

关键词： Hardware Software Object oriented modeling Microcontrollers Java Emulation Computer architecture

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A chaos-based pseudo-random bit generator implemented in FPGA device

A chaos-based pseudo-random bit generator implemented in FPG...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Pawel Dabal Ryszard Pelka Department of Electronic Engineering Military University of Technology Warsaw Poland

this paper presents results of studies on the implementation of pseudo-random bit generators based on a nonlinear dynamic chaotic system. Several solutions have been investigated, using different computing precision and various implementation of arithmetic operations. the results of the second level NIST tests for randomness of the proposed pseudo-random bit generators (PRBGs) are presented, that proved good cryptographic properties of the presented PRBGs. the generators described in this paper can be used for key generation in stream ciphers in secure, real-time transmission of digital signals, including audio-video applications.

关键词： Generators Chaotic communication Cryptography NIST Logistics Field programmable gate arrays

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Decreasing test time by scan chain reorganization

Decreasing test time by scan chain reorganization

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Pavel Bartoš Zdeněk Kotásek Jan Dohnal Faculty of Information Technology Brno University of Technology Brno Czech Republic ON Design Czech s. r. o. (On Semiconductor) Brno Czech Republic

In this paper, methodology for scan chain optimisation performed after physical layout is presented. It is shown how the methodology can be used to decrease test time of component under test if scan chain is reorganized. the principles of the methodology are based on eliminating some types of faults in the physical layout and subsequent reduction of the number of test vectors needed to test the scan chain. As a result, component test application time is decreased. the methodology was verified on several circuits, experimental results are provided and discussed. It is expected that the results of our methodology can be used in mass production of electronic components where any reduction of test time is of great importance.

关键词： Circuit faults Wires Optimization Layout Integrated circuit interconnections electronic components Testing

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design-for-Test method for high-speed ADCs: Behavioral description and optimization

Design-for-Test method for high-speed ADCs: Behavioral descr...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Y. Lechuga R. Mozuelos M. Martínez S. Bracho Microelectronics Engineering Group University of Cantabria Santander Spain

this paper presents a design-for-Test (DfT) approach for folded analog to digital converters. A sensor circuit is designed to sample several internal ADC test points at the same time, so that, by computing the relative deviation among them the presence of a defect can be detected. A fault evaluation is carried out on a behavioral model to compare the coverage of the proposed test approach with the one obtained from a functional test. then, the analysis is moved to a transistor level implementation of the ADC to establish the threshold limits for the DfT circuit that maximize the fault coverage figure of the test approach.

关键词： Circuit faults Preamplifiers Transistors Resistors Integrated circuit modeling Bandwidth Computational modeling

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Manufacturing variability analysis in Carbon Nanotube Technology: A comparison with bulk CMOS in 6T SRAM scenario

Manufacturing variability analysis in Carbon Nanotube Techno...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Carmen García Antonio Rubio Electronic Engineering Department BarcelonaTECH UPC Barcelona Spain

In silicon bulk CMOS technology the variability of the device parameters is a key drawback that may be a limiting factor for further miniaturizing nodes. New nanoscale beyond-CMOS devices are being studied such as carbon nanotubes (CNTs). the goal of this paper is to evaluate the parameter variability in Carbon Nanotube Field Effect Transistors (CNFETs) and its potential capability to be a promising alternative to Si-CMOS technology. the impact of the carbon nanotube diameter variations as well as the presence of metallic carbon nanotubes in the transistor are analyzed (device level). this variability model is used to make a comparison between Si-MOSFET and CNFET Static Random Access Memory (SRAM) 6T cells (circuit level).

关键词： CNTFETs Random access memory CMOS integrated circuits Electron tubes CMOS technology Power demand

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Behavior of CMOS polymorphic circuits in high temperature environment

Behavior of CMOS polymorphic circuits in high temperature en...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Richard Ruzicka Vaclav Simek Lukas Sekanina Faculty of Information Technology Brno University of Technology Brno Czech Republic

the paper describes a series of experiments performed with the aim to analyze the fundamental impact of high temperatures on behavior of polymorphic digital circuits. these experiments were conducted using a reconfigurable polymorphic chip REPOMO32 which is configured (in addition to the configuration bit stream) using the level of power supply voltage (V dd ). Experiments show that polymorphic gates in the chip can be easily involved (in terms of functionality) not only by V dd , but also by temperature. Because experiments also prove that the physical design of the REPOMO32 chip is robust enough to keep the functionality of all circuitry of the REPOMO32 and its dynamic parameters are stable enough under wide range of operating temperature, the chip can also be used for future designs of digital polymorphic circuits controlled by temperature.

关键词： Logic gates Heating Temperature sensors Transistors Power supplies Logic functions Switches

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