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Defect-oriented module-level fault diagnosis in digital circuits

Defect-oriented module-level fault diagnosis in digital circ...

引用

ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Sergei Kostin Raimund Ubar Jaan Raik Department of Computer Engineering Tallinn University of Technology Estonia

We propose a hierarchical approach for physical defect diagnosis in combinational or full scan-path digital circuits represented as module networks. As modules we may consider arbitrary subcircuits or library components (e.g. complex gates) of digital circuits. Both, cause-effect and effect-cause approaches are exploited intermittently. the higher level fault diagnosis is carried out in two phases. In the first phase, faulty modules are located by cause-effect analysis using high-level faulty module dictionary. the size of the dictionary depends linearly on the number of modules in the circuit. In the second phase, the set of suspected faulty modules is pruned by effect-cause indirect defect reasoning. At the lower level, the physical defects are directly located in suspected faulty modules. the proposed approach to fault diagnosis helps to cope with the growing complexities of digital circuits. the experimental results show high diagnostic resolution of the proposed approach.

关键词： Circuit faults Dictionaries Fault diagnosis Integrated circuit modeling Cognition Libraries Logic gates

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Test vector overlapping based compression tool for narrow test access mechanism

Test vector overlapping based compression tool for narrow te...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Jiří Jeníček Martin Rozkovec Ondřej Novák Technical University of Liberec Liberec Czech Republic

this paper describes an algorithm, which utilizes a test data compression method based on test vector overlapping to compact and compress test patterns. the algorithm takes deterministic test vectors previously generated in an ATPG and compresses them by reordering and overlapping them. It is able to speed up the test generation process by using distributed ATPG processing and compress test data for various fault models. Independency of the algorithm on used ATPG is discussed and verified, the compressor is able to cooperate with industry workflow tools using Verilog and STIL formats. the compressor preprocesses the input data to determine the degree of random test resistance for each fault. this optional step allows to rearrange the test vectors more efficiently and results to 10% compression ratio improvement in average.

关键词： Circuit faults Automatic test pattern generation Resistance Integrated circuit modeling Algorithm design and analysis Encoding

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An analog perspective on device reliability in 32nm high-κ metal gate technology

An analog perspective on device reliability in 32nm high-κ ...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Florian Raoul Chouard Shailesh More Michael Fulde Doris Schmitt-Landsiedel Lehrstuhl für Technische Elektronik Technische Universität München Munchen Germany Intel Mobile Communications GmbH Villach Austria

An assessment on analog circuit reliability for an advanced 32nm high-κ metal gate technology is given from the analog designer's point of view. Selected analog circuit blocks are investigated with respect to device stress states. A custom test structure, designed to reveal analog related device characteristics including relaxation effects, was used to perform stress measurements. In addition to common aging in inversion mode, degradation in accumulation mode is determined. Experiments reveal that relaxation shows a large variety in drift behavior, and degradation induced variations - even for analog size devices - can reach significant values. Both topics are main issues for analog circuits design. thereupon a general approach to consider device aging for analog circuit reliability is proposed.

关键词： Stress Degradation Aging MOS devices Annealing Analog circuits Transistors

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Fast just-in-time translated simulator for ASIP design

Fast just-in-time translated simulator for ASIP design

引用

ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Zdeněk Přikryl Jakub Křoustek Tomáš Hruška Dušan Kolář Faculty of Information Technology Brno University of Technology Brno Czech Republic

the fast and accurate processor simulator is an essential tool for effective design of modern high-performance application-specific instruction set processors. the nowadays trend of ASIP design is focused on automatic simulator generation based on a processor description in an architecture description language. the simulator is used for testing and validation of designed processor or target application. Furthermore, the simulator can produce the profiling information. this information can aid design space exploration and the processor and target application optimization. In this paper, we present the concept of automatically generated just-in-time translated simulator with the profiling capabilities. this simulator is very fast, and it is generated in a short time. It can be even used for simulation of special applications, such as applications with self-modifying code or applications for systems with external memories. the experimental results can be found at the end of the paper.

关键词： Analytical models Testing Optimization Computer architecture Conferences VLIW Computational modeling

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Low-power quadrature VCO design for medical implant communication service

Low-power quadrature VCO design for medical implant communic...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Jeong Ki Kim Jihoon Jeong Dong Sam Ha Hyung-soo Lee Bradley Department of Electrical and Computer Eng Virginia Polytechnic Institute and State University Blacksburg VA USA Green Computing Research Division Electronics and Telecommunications Research Institute Daejeon South Korea

this paper presents two different implementations of a low-power quadrature frequency source generator for medical implant communication service (MICS) applications. the first circuit uses a current-reuse VCO running at double the target frequency followed by a divide-by-two frequency divider. the circuit dissipates only 230 μW and achieves low phase noise of -127 dBc/Hz@1MHz. the second one adopts a parallel-coupling scheme to combine two current-reuse VCOs (P-QVCO). the circuit exhibits a moderate power consumption of 960 μW and achieves very low phase noise of -138 dBc/Hz@1MHz.

关键词： Voltage-controlled oscillators Phase noise Resistors Microwave integrated circuits Power demand Damping Couplings

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Wireless wafer-level testing of integrated circuits via capacitively-coupled channels

Wireless wafer-level testing of integrated circuits via capa...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Dae Young Lee David D. Wentzloff John P. Hayes Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

Wafer testing via direct-contact probe cards has long been an effective and relatively low-cost method for testing integrated circuit (IC) chips prior to packaging. However, the physical contact occurring between the wafer and automatic test equipment (ATE) has significant costs due to contact point deformation and the need for abrasive cleaning. In this paper, we investigate a non-contact testing technique that wirelessly couples an IC wafer and ATE, and serves as an alternative to conventional probe-card testing. We derive several analytical models for a capacitive testing channel. Electromagnetic field simulations results are presented that support the proposed channel models. We conclude that capacitance-based wireless testing is feasible for testing ICs in the 1-GHz range.

关键词： Couplings Testing Capacitance Wireless communication Metals Gain System-on-a-chip

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Precise IPv4/IPv6 packet generator based on NetCOPE platform

Precise IPv4/IPv6 packet generator based on NetCOPE platform

引用

ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Jiří Matoušek Pavol Korček Faculty of Information Technology Brno University of Technology Brno Czech Republic

this paper presents an architecture of a hardware network packet generator designed for the COMBOv2 cards using the NetCOPE development platform. the packet generator internal structure allows synthetic IPv4 and IPv6 network packet creation as well as the real network packet transmission. Based on COMBOv2 add-on interface card, the generator is able to transmit packets at speed of 2×10 Gbit/s or 4×1 Gbit/s. Synthetic data are created using high quality pseudo-random number generator. If desired, previously captured network packets can be transmitted back to the network with exactly the same time drift as were captured. this is accomplished by extremely precise timestamps, which can be generated by the Timestamp Module included in the NetCOPE platform.

关键词： Field programmable gate arrays Generators Switches Driver circuits Registers Limiting Radiation detectors

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Effective hash-based IPv6 longest prefix match

Effective hash-based IPv6 longest prefix match

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Jiří Tobola Jan Kořenek Faculty of Information Technology Brno University of Technology Brno Czech Republic

With the growing speed of computer networks, the core routers have to increase performance of longest prefix match (LPM) operation on IP address. While existing LPM algorithms are able to achieve high throughput for IPv4 addresses, the IPv6 processing speed is limited. In this paper we propose a new Hast-Tree Bitmap algorithm for fast longest prefix match for both IPv4 and IPv6 networks. the algorithm is able to achieve high throughput for a long IPv6 addresses by fast hash function which is used to jump over the sparse part of the IP prefix tree. the proposed algorithm was mapped to the highly pipelined hardware architecture, which offers well balanced resource requirements for IPv6 look-up and is able to achieve a wire-speed throughput for 100 Gbps networks.

关键词： throughput Hardware IP networks Memory management Field programmable gate arrays Algorithm design and analysis Engines

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Hardware architecture for packet classification with prefix coloring

Hardware architecture for packet classification with prefix ...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Viktor Puš Michal Kajan Jan KoŸenek Faculty of Information Technology Brno University of Technology Brno Czech Republic

Packet classification is a widely used operation in network security devices. As network speeds are increasing, the demand for hardware acceleration of packet classification in FPGAs or ASICs is growing. Nowadays algorithms implemented in hardware can achieve multigigabit speeds, but suffer with great memory overhead. We propose a new algorithm and hardware architecture which reduces memory requirements of decomposition based methods for packet classification. the algorithm uses prefix coloring to reduce large amount of Cartesian product rules at the cost of an additional pipelined processing and a few bits added into results of the longest prefix match operation. the proposed hardware architecture is designed as a processing pipeline with the throughput of 266 million packets per second using commodity FPGA and one external memory. the greatest strength of the algorithm is the constant time complexity of the search operation, which makes the solution resistant to various classes of network security attacks.

关键词： Image color analysis Color Memory management Hardware Field programmable gate arrays Algorithm design and analysis

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A system-level platform for dependability enhancement and its analysis for mixed-signal SoCs

A system-level platform for dependability enhancement and it...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Muhammad A. Khan Hans G. Kerkhoff Testable Design and Test of Integrated Systems (TDT) Group Centre of Telematics and Information Technology (CTIT) University of Twente Enschede Netherlands

the long-term functionality of any electronic system poses some requirements on the dependability of that system. Especially for critical systems it is becoming a crucial property with increasing system complexity and shrinking technology dimensions. Analog and mixed-signal systems are an important part of these critical systems. Until now little effort has been put into dependability of analog and mixed-signal systems, especially front/back-ends. this paper presents a new system-level platform for enhancing and analyzing the dependability of analog and mixed-signal front-ends in SoCs. Markov analysis has been used to theoretically investigate the dependability enhancement of these analog and mixed-signal front-ends based on this platform. Simulations in VHDL-AMS have also been conducted for an example target system consisting of a temperature sensor, operational amplifier and ADC to illustrate this platform. the gain parameter of the whole system, taken as an example of potential dependability hazard, has been investigated and enhanced based on this platform. the results show that this proposed platform is effective and has the potential to investigate and enhance dependability at system level.

关键词： Markov processes Maintenance engineering Tuning Availability Mathematical model Analytical models

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