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检索条件"任意字段=13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

共 683 条记录，以下是531-540 订阅

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A Build-In Self-Test Technique for RF Mixers

A Build-In Self-Test Technique for RF Mixers

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13th ieee symposium on design and diagnostics of electronic circuits and systems

作者： Dermentzoglou, Lambros Arapoyanni, Angela Tsiatouhas, Yiorgos Univ Athens Dept Informat & Telecommun Athens Greece Univ Ioannina Dept Comp Sci Ioannina Greece

ISBN: (纸本)9781424466139

A Build-In Self-Test (BiST) circuit suitable for embedded RF Mixers in System-on-Chip applications is presented in this paper. this is a defect-oriented test scheme that dynamically sets the Mixer to operate in homodyne mode. the DC level generated at its output is used to control the oscillation frequency of a simple voltage controlled oscillator. Deviations of the oscillation frequency from the expected range of values indicate a defective Mixer. the proposed BiST technique has been applied to a typical receiver's differential RF Mixer using a 0.35 mu m CMOS technology. Simulation results validated the efficiency of the BiST circuit which was capable to provide a high fault coverage of catastrophic faults (which exceeds 91%) and a small test application time (1 mu s), at a silicon area cost approximately 16% of the Mixer area.

关键词： Build-in-Self Test design for Testability RF Mixer Defect Based Testing

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Computation Reduction for Statistical Analysis of the Effect of nano-CMOS Variability on Asynchronous circuits

Computation Reduction for Statistical Analysis of the Effect...

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13th ieee symposium on design and diagnostics of electronic circuits and systems

作者： Xie, Zheng Edwards, Doug Univ Manchester Sch Comp Sci Manchester M13 9PL Lancs England

ISBN: (纸本)9781424466139

the intrinsic atomistic variability of nano-scale integrated circuit (IC) technology must be taken into account when analyzing circuit designs to predict likely yield. Monte Carlo (MC) based statistical techniques aim to do this by analysing many randomized copies of the circuit. A major problem is the computational cost of carrying out sufficient analyses to produce statistically reliable results. the MC analyses required for asynchronous circuits are more difficult than are generally required for clocked circuits because of the more complex timing patterns created by handshaking mechanisms. It is important to reduce the computational complexity of MC analysis required for asynchronous circuits. the use of 'Statistical Behavioural Circuit Blocks (SBCB)' is investigated as a means of reducing the dimensionality of the analysis, and this is combined with an implementation of 'Statistical Blockade' to achieve significant reduction in the computational costs. the reduction in computation time achieved by the more efficient MC analysis is illustrated by statistically analysing several simple handshaking circuits.

关键词： nano-scale integrated circuit variability Monte Carlo (MC) statistical techniques Statistical Behavioural Circuit Block Statistical Blockade asynchronous circuit

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On Logic Synthesis of Conventionally Hard to Synthesize circuits Using Genetic Programming

On Logic Synthesis of Conventionally Hard to Synthesize Circ...

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13th ieee symposium on design and diagnostics of electronic circuits and systems

作者： Fiser, Petr Schmidt, Jan Vasicek, Zdenek Sekanina, Lukas Czech Tech Univ Fac Informat Technol Prague Czech Republic Brno Univ Technol Fac Informat Technol Brno Czech Republic

ISBN: (纸本)9781424466139

Recently, it has been shown that synthesis of some circuits is quite difficult for conventional methods. In this paper we present a method of minimization of multi-level logic networks which can solve these difficult circuit instances. the synthesis problem is transformed on the search problem. A search algorithm called Cartesian genetic programming (CGP) is applied to synthesize various difficult circuits. Conventional circuit synthesis usually fails for these difficult circuits;specific synthesis processes must be employed to obtain satisfactory results. We have found that CGP is able to implicitly discover new efficient circuit structures. thus, it is able to optimize circuits universally, regardless their structure. the circuit optimization by CGP has been found especially efficient when applied to circuits already optimized by a conventional synthesis. the total runtime is reduced, while the result quality is improved further more.

关键词： logic synthesis multi-level network genetic programming

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Buffer-Ring-Based All-Digital On-Chip Monitor for PMOS and NMOS Process Variability and Aging Effects

Buffer-Ring-Based All-Digital On-Chip Monitor for PMOS and N...

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13th ieee symposium on design and diagnostics of electronic circuits and systems

作者： Iizuka, Tetsuya Nakura, Toru Asada, Kunihiro Univ Tokyo VLSI Design & Educ Ctr VDEC Bunkyo Ku 7-3-1 Hongo Tokyo Japan Univ Tokyo Dept Elect Engn & Informat Syst Bunkyo Ku Tokyo 1138656 Japan

ISBN: (纸本)9781424466139

In this paper, we propose an all-digital process variability and aging monitor which utilizes a simple buffer ring with a pulse counter. the proposed circuit monitors the process variability according to a count number of a single pulse which propagates on the buffer ring and a fixed logic level after the pulse vanishes. Using the proposed circuit in combination with a simple ring oscillator which monitors its oscillation period, we can calculate the rise and fall delay values and can monitors the variabilities of PMOS and NMOS devices independently. the experimental results of the circuit simulation on 65nm CMOS process indicate the feasibility of the proposed monitoring circuit. the proposed monitoring technique is suitable not only for the on-chip process variability monitoring but also for the infield monitoring of aging effects such as negative bias instability (NBTI) and channel hot carrier (CHC).

关键词： Circuit simulation

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On the Mitigation of SET broadening effects in Integrated circuits

On the Mitigation of SET broadening effects in Integrated Ci...

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13th ieee symposium on design and diagnostics of electronic circuits and systems

作者： Sterpone, Luca Battezzati, Niccolo Politecn Torino Dip Automat & Informat Turin Italy

ISBN: (纸本)9781424466139

Nowadays, the integrated circuits design and manufacturing process are decreasing the minimum transistor size and this advancement, accompanied by increasing operating frequencies and lower power supplies voltages, leads, on the one side, to the availability of fast and low power circuits with very small noise margins but, on the other side, makes integrated circuits more sensitive to Single Event Transient (SET) pulses that may be generated and propagated through the combinational logic, leading to misbehaviors. SETs are mainly generated by high-energy particles that strikes the circtuit near a junction, resulting in a significant charge injection/depletion process, that may produce spurious pulses. these can propagate and change their shape traversing the combinational logic paths, sometimes being broadened and amplified sometimes being filtered. In this paper, we present a place and route algorithm for integrated circuit design, which is able to mitigate and filter the erroneous effects of SETs. the proposed solution has been experimentally evaluated by means of electrical pulse injection within logic resources of several benchmark Integrated circuits (ICs) implemented in a Flash-based FPGA and by accurate timing analyses. Preliminary results confirm the mitigation of SET broadening effects by acting on physical place and route constraints. On the selected benchmark circuit the algorithm decreases the SET sensitiveness more than 70% with respect to not hardened circuits. Besides, the solution does not introduce any area overhead or delay penalties.

关键词： Integrated circuit design

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Automated Simulation-based Verification of Power Requirements for systems-on-Chips

Automated Simulation-based Verification of Power Requirement...

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13th ieee symposium on design and diagnostics of electronic circuits and systems

作者： Trummer, Christoph Kirchsteiger, Christoph M. Steger, Christian Weiss, Reinhold Pistauer, Markus Dalton, Damian Graz Univ Technol Inst Tech Informat Graz Austria CISC Semicond Design Consulting GmbH Klagenfurt Austria Univ Coll Dublin Sch Comp Sci & Informat Dublin Ireland

ISBN: (纸本)9781424466139

Today power dissipation is the most important constraint for systems-on-Chips (SoCs). Consequently, it is necessary to consider power in the requirements of mobile, battery-powered devices in which SoCs are often used. these power requirements describe battery lifetime, power constraints and low-power states. Verification ensures that the system fulfills the power requirements. However, verifying all requirements of the complex SoC design needs considerable effort. We introduce a methodology(1) to reduce the verification effort through a high degree of automation. Our novel approach to verify battery lifetime, power constraints and the power aware design comprises three parts. First, a semi-formal use case format unifies specification of power and system requirements. Second, these specifications are used to automatically derive test cases and to generate a verification environment. third, fast simulation and power estimation are employed to verify battery lifetime, power constraints and the power aware design against the requirements.

关键词： System-on-chip

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design of a Single Layer Programmable Structured ASIC Library

Design of a Single Layer Programmable Structured ASIC Librar...

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13th ieee symposium on design and diagnostics of electronic circuits and systems

作者： Chau, thomas C. P. Wu, David W. L. Ai, Yan-Qing Chan, Brian P. W. Ho, Sam M. H. Lau, Oscar K. L. Yuen, Steve C. L. Pun, Kong-Pang Choy, Oliver C. S. Leong, Philip H. W. Chinese Univ Hong Kong Dept Comp Sci & Engn Hong Kong Hong Kong Peoples R China Chinese Univ Hong Kong Dept Elect Engn Hong Kong Hong Kong Peoples R China Univ Sydney Sch Elect & Informat Engn Sydney NSW Australia

ISBN: (纸本)9781424466139

A Structured Application-specific Integrated Circuit (SASIC) is a programmable fabric in which a small set of masks are customized for a particular application, serving to reduce the associated non-recurring engineering cost (NRE). In this paper we describe the implementation of a SASIC logic cell which is programmable via a single metal layer. A SASIC fabric prototype is fabricated and all implemented functions are verified on silicon. Experimental measurement verifies correct operation of our SASIC with a clock frequency of over 250MHz.

关键词： application specific integrated circuits digital integrated circuits field programmable gate arrays

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Intelligent IGBT driver concept or three-phase electric drive diagnostics

Intelligent IGBT driver concept or three-phase electric driv...

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13th ieee International symposium on design and diagnostics of electronic circuits and systems, DDECS 2010

作者： Klima, B. Knobloch, J. Pochyla, M. Department of Power Electrical and Electronic Engineering Faculty of Electrical Engineering and Communication Brno University of Technology Brno Czech Republic

ISBN: (纸本)9781424466139

this document focuses on he problem of diagnostics of an electrical drive equipped with a voltage source inverter (VSI) the attention is concentrated on a hardware design or a power system diagnostics A new concept of a power transistor driver is proposed. this concept of he driver integrates functions for monitoring of a large number of electrical drive parameters which are transferred to the superior control system for an actual operation state evaluation or an eventual failure state detection. the proposed solution introduces the possibility of an internal electrical quantities feedback realization (phase currents and DC link voltage) directly in the drivers of power transistors without using standard current and voltage sensors the feed-backs can be extended with output voltages measurement of the inverter which can be further used in online identification of motor parameters for a model of the electrical drive. this model can be used for a control technique adaptation (with respect to maximal efficiency, maximal dynamic performance or also or sensor-less peed control or position control). © 2010 ieee.

关键词： Insulated gate bipolar transistors (IGBT)

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A hardware accelerated framework for the generation of design validation programs for SMT processors

A hardware accelerated framework for the generation of desig...

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13th ieee International symposium on design and diagnostics of electronic circuits and systems, DDECS 2010

作者： Ravotto, D. Sánchez, E. Sonza Reorda, M. Politecnico di Torino Dipartimento di Automatica e Informatica Torino Italy

ISBN: (纸本)9781424466139

In this paper, we propose an innovative emulation-based framework for the generation of test programs oriented to SMT microprocessor validation. the two major characteristics of the proposed framework are an effective method to gather information about the processor internal status via its emulation, and an efficient algorithm which exploits these pieces of information for a generation process which is particularly suited for SMT processors. Performance counters (PCs) as well as ad hoc registers are used to achieve the former result, while a feedback-based generation process is devised to achieve the latter. Experimental results gathered on a real complex design (the OpenSPARC™ T1 core) show that the proposed framework can achieve high quality results with acceptable CPU time and human effort requirements. © 2010 ieee.

关键词： Software testing

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Versatile sub-bandgap reference IP core

Versatile sub-bandgap reference IP core

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13th ieee International symposium on design and diagnostics of electronic circuits and systems, DDECS 2010

作者： Urban, Tomáš Šubrt, Ondřej Martinek, Pravoslav Department of Circuit Theory Faculty of Electrical Engineering CTU Prague Technická 2 166 27 Prague Czech Republic ASICentrum Novodvorská 994 142 21 Prague Czech Republic

ISBN: (纸本)9781424466139

A step-by-step design procedure of sub-bandgap voltage reference (BGR) is proposed. the procedure shows on example structure main design steps of crucial parameters verified later by a simulation. the block is meant to be fabricated in 0.35μm CMOS process with analog options. the main features of the concept are the sub-bandgap output voltage of 0.7V, low supply voltage from 1.3V, low power consumption under 10μA, versatility, high working temperature range from -50 to 95°C. the versatility of the block is supported by a temperature slope trimming, extended start-up and self testing. the IP block is compact, ready to adjust, layout and integrate. the features of the design also allow the in circuit tuning. this example circuit shows the use of the design algorithm including the optimization suggestions which lead to a complex design. © 2010 ieee.

关键词： design

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