Flexible Application Specific Instruction set Processors (ASIP) are starting to replace monolithic ASICs in a wide variety of fields. However the construction of an ASIP is today associated with a substantial design e...
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Cryptographic algorithms are used to protect sensitive information when the communication medium is not secure. Unfortunately, the hardware implementation of these cryptographic algorithms allows secret key retrieval ...
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Quasi Delay Insensitive asynchronous logic is a very robust system allowing safe implementations while requiring minimal timing assumptions. Unfortunately the design methodologies using this system have always yielded...
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ISBN:
(纸本)9781424433391
Quasi Delay Insensitive asynchronous logic is a very robust system allowing safe implementations while requiring minimal timing assumptions. Unfortunately the design methodologies using this system have always yielded very slow designs. Early output logic is a method which aims to improve the performance of QDI circuits without decreasing their robustness. In order to force QDI restrictions on early output circuits a form of guarding is necessary. this paper presents a new form of guarding which allows partial stage completion allowing desynchronisation of inputs. this is shown to be highly advantageous in cases where the previous style performed poorly. Because the two styles can be mixed, the designs no longer suffer from very poor performance of some QDI constructions.
Self-timed full adder designs based on commercial synchronous resources (standard cells), constructed using a mix of complete delay-insensitive codes adopted for inputs are described in this paper. While one of the ad...
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ISBN:
(纸本)9781424433391
Self-timed full adder designs based on commercial synchronous resources (standard cells), constructed using a mix of complete delay-insensitive codes adopted for inputs are described in this paper. While one of the adder designs incorporates redundancy into the logic, the other design does not. Comparisons have been carried out with respect to various self-timed full adder designs which employ only a single widely used delay-insensitive input encoding for boththe inputs and outputs. It has been found out from exhaustive simulations that incorporating redundancy into the logic actually benefits in terms of delay, but a non-redundant implementation proves to be beneficial with respect to power and area parameters.
Model checking of assembly code is a promising approach to satisfy the demand for verification in nowadays ultra-high reliable embedded systems software. Frequent interaction with its environment, e.g., by sending or ...
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ISBN:
(纸本)9781424433391
Model checking of assembly code is a promising approach to satisfy the demand for verification in nowadays ultra-high reliable embedded systems software. Frequent interaction with its environment, e.g., by sending or reading data over the microcontroller's I/O lines, lies in the nature of embedded systems. thus, making the long-standing problem of explicit-model checking even worse, namely the state-explosion problem. this paper presents a concept to tackle these difficulties by using a 3-valued logic in the state representation and showing its benefits in terms of state-space savings whenever logic operations are executed by the target microcontroller. To highlight the effectiveness of this approach, termed delayed nondeterminisnt with look ahead, an embedded program exemplifying typical microcontroller source code is analyzed and the resulting state space sizes are discussed. the introduced abstraction technique is implemented in the MCS-51 simulator component for the [mc]square model checker which is developed by the RWth Aachen University.
this paper describes VSYML, a symbolic simulator that extracts formal models from VHDL descriptions. the generated models are adequate to formal reasoning in various frameworks. VSYML is a reimplementation of its ance...
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this paper describes VSYML, a symbolic simulator that extracts formal models from VHDL descriptions. the generated models are adequate to formal reasoning in various frameworks. VSYML is a reimplementation of its ancestor theosim; it brings various improvements e.g., with regard to arrays and other complex data types.
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