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检索条件"任意字段=13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

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A symbolic RTL synthesis for LUT-based FPGAs

A symbolic RTL synthesis for LUT-based FPGAs

引用

ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Stanislaw Deniziak Mariusz Wisniewski Department of Computer Engineering Cracow University of Technology Cracow Poland Department of Computer Science Kielce University of Technology Kielce Poland

In this paper a methodology of symbolic RTL synthesis, for circuits implemented in FPGA devices, is presented. First, symbolic functions are separated from binary and arithmetic ones. Next, the multi-valued logic network is optimized using our methods of symbolic functional decomposition, designed for functions with multi-valued inputs and multi-valued outputs. Finally, the whole circuit is implemented in FPGA device using commercially available tools. the goal of the presented methodology is to minimize the total FPGA area. Presented example showed that our methodology gives better results than existing RTL synthesis tools.

关键词： Field programmable gate arrays Network synthesis Circuit synthesis Optimization methods Encoding Signal synthesis Multivalued logic Arithmetic design optimization Algebra

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Low-voltage low-power double bulk mixer for direct conversion receiver in 65nm CMOS

Low-voltage low-power double bulk mixer for direct conversio...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Kurt Schweiger Heimo Uhrmann Horst Zimmermann Institute of Electrical Measurements and Circuit Design University of Technology Vienna Vienna Austria

An innovative design with simulation results of a low-voltage bulk driven mixer for direct conversion receiver is presented. the circuit is designed in a 65 nm digital CMOS process without analog extensions. It offers a conversion gain of 22 dB at a clock frequency of 1.5 GHz for GALILEO/GPS applications. the design is capable of operating at up to 7 GHz with only 3 dB gain decrease. the simulated noise figure is 27 dB with a power consumption of 730 muW. Simulations at a supply voltage of 0.9 V instead of 1.2 V show a gain decrease of only 3 dB while the noise figure increases by 2 dB.

关键词： Gain Noise figure Circuit simulation Mixers CMOS process Clocks Frequency conversion Global Positioning System Energy consumption Voltage

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An utilisation of Boolean differential calculus in variables partition calculation for decomposition of logic functions

An utilisation of Boolean differential calculus in variables...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Stefan Kolodzinski Edward Hrynkiewicz Pratt and Whitney Kalisz Poland Institute of Electronics Silesian University of Technology Gliwice Poland

the paper deals with the problems of input variables assigning to the free and bounded sets during logic function decomposition. the Ashenhurst decomposition is considered with respect to implementation of logic functions in LUT based FPGA. the method of finding profitable input variables partitioning is based on utilisation of Logic Differential Calculus. the elaborated method is very convenient especially if decomposition is carried out in Reed-Muller spectral domain because the Boolean differentials are easy calculated from Reed-Muller form of logic function which is simply calculated as reverse Reed-Muller transform. the obtained results are very promising.

关键词： Calculus Logic functions Input variables Field programmable gate arrays Boolean functions Table lookup Paper technology design methodology Manufacturing Logic devices

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A fast untestability proof for SAT-based ATPG

A fast untestability proof for SAT-based ATPG

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Daniel Tille Rolf Drechsler Institute of Computer Science University of Brethemen Bremen Germany

Automatic Test Pattern Generation (ATPG) based on Boolean satisfiability (SAT) has been shown to be a beneficial complement to traditional ATPG techniques. SAT solvers work on instances given in Conjunctive Normal Form (CNF). the required transformation of the ATPG problem into CNF is one main part of SAT-based ATPG and needs a significant portion of the overall run time. Solving the SAT instance is the other main part. Here, the time needed is often negligible - especially for easy-to-classify untestable faults. this paper presents a preprocessing technique that speeds up the classification of untestable faults by accelerating the SAT instance generation. this increases the robustness of the entire ATPG process. the efficiency of the proposed method is shown by experiments on large industrial designs.

关键词： Automatic test pattern generation Circuit faults Circuit testing Robustness Test pattern generators Acceleration electronic design automation and methodology Buildings Computer science Circuit synthesis

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0.5V 160-MHz 260uW all digital phase-locked loop

0.5V 160-MHz 260uW all digital phase-locked loop

引用

ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Jen-Chieh Liu Hong-Yi Huang Wei-Bin Yang Kuo-Hsing Cheng Department of Electrical Engineering National Central University Taiwan Graduate Institute of Electrical Engineering National Taipei University Taiwan Department of Electrical Engineering Tamkang University Taiwan

A low power all-digital phase locked-loop (ADPLL) in a 0.13um CMOS process is presented. the pulse-based digitally controlled oscillator (PB-DCO) performs a high resolution and wide range. the locking time of ADPLL is less then 32 reference clock cycles. the multiplication factor is 2 to 63. Power consumption is 260uW at 160-MHz and 80uW at 60-MHz with 0.5V supply voltage.

关键词： Phase locked loops Frequency Clocks Jitter Circuit optimization Voltage Counting circuits Digital control Energy consumption Microprocessors

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Round-level concurrent error detection applied to Advanced Encryption Standard

Round-level concurrent error detection applied to Advanced E...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Flavius Opritoiu Mircea Vladutiu Mihai Udrescu Lucian Prodan Polytechnic University of Timisoara Timisoara Romania

this paper presents a hardware architecture for online self-test in the context of Advanced Encryption Standard (AES). From the available range of techniques and solutions to be considered for increasing Built In Self-Test (BIST) capabilities, for various reasons - especially due to area requirements - we focused on parity control methods. therefore, the paper presents a general solution proposing both a basic architecture and a new project designed at the gate level that relies on parity prediction techniques. the contribution brought by our architecture consists of a complete separation between the functional and test channels. the conclusive arguments reveal the proposed architecture as a solution for area reduction; performance and power consumption are also analyzed.

关键词： Cryptography Hardware Built-in self-test Computer architecture Testing Power system security Information security Costs electronic mail Energy consumption

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Optimization concepts for self-healing asynchronous circuits

Optimization concepts for self-healing asynchronous circuits

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： thomas Panhofer Werner Friesenbichler Martin Delvai RUAG Aerospace Austria Institute of Computer Engineering University of Technology Vienna Austria

Decreasing feature size and lower supply voltage cause integrated circuits to be more error-prone, during production as well as during runtime. At the same time the demand for higher reliability is increasing. In particular for applications with long mission times and where no repair is possible, complex fault tolerance mechanisms are required, leading to a dramatic increase of design and system costs. Runtime reconfiguration seems to be a promising way to obtain a circuit which is able to handle these challenges. In previous papers we presented a self-healing approach based on asynchronous Four-State Logic (FSL) and using reconfigurable circuit elements, called Self-Healing Cells (SHCs). these SHCs allow to bypass defect resources and to recover from multiple permanent faults. While the combinational logic can be easily reconfigured this way, the application of SHCs in an asynchronous pipeline requires special treatment of the handshake signals. In this paper we present a self-healing pipeline architecture and analyse different SHC architectures with respect to resource occupation, fault tolerance and reconfiguration speed.

关键词： Asynchronous circuits Runtime Reconfigurable logic Pipelines Voltage Production Integrated circuit reliability Fault tolerant systems Costs Logic circuits

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An efficient fault simulation technique for transition faults in non-scan sequential circuits

An efficient fault simulation technique for transition fault...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： A. Bosio P. Girard S. Pravossoudovich P. Bernardi M. Sonza Reorda LIRMM CNRS Université de Montpellier II Montpellier France Dipartimento di Automatica e Informatica Politecnico di Torino Torino Italy

this paper proposes an efficient technique for transition delay fault coverage measurement in synchronous sequential circuits. the proposed strategy is based on a combination of multi-valued algebra simulation, critical path tracing and deductive fault simulation. the main advantages of the proposed approach are that it is highly computationally efficient with respect to state-of-the-art fault simulation techniques, and that it encompasses different delay sizes in one simulation pass without resorting to an improved transition fault model. Preliminary results on ITC99 benchmarks show that the gain in terms of CPU time is up to one order of magnitude compared to previous existing techniques.

关键词： Circuit faults Circuit simulation Sequential circuits Circuit testing Delay Clocks Sequential analysis Computational modeling Automatic testing Central Processing Unit

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Physical design oriented DRAM Neighborhood Pattern Sensitive Fault testing

Physical design oriented DRAM Neighborhood Pattern Sensitive...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Yiorgos Sfikas Yiorgos Tsiatouhas Department of Computer Science University of Ioannina (UoI) Ioannina Greece

Although the Neighborhood Pattern Sensitive Fault (NPSF) model is recognized as a high quality fault model for memory arrays, the excessive test application time cost associated with it, compared to other fault models, restricts its wide adoption for memory testing. In this work we exploit the physical design (layout) of folded DRAM memory arrays to introduce a new neighborhood type for NPSF testing and a pertinent test and locate algorithm. this algorithm reduces drastically the test application time (about 58% with respect to the well known Type-1 neighborhood) aiming to make the NPSF model also a cost attractive choice. In addition, we introduce the Neighborhood Word-Line Sensitive Fault model and the corresponding test algorithm to cover those faults along with NPSFs, achieving test application time cost reduction from 33% to 41%, depending on various assumptions, with respect to the Type-1 neighborhood.

关键词： Random access memory Testing Costs Computer science Pattern recognition Application software Algorithm design and analysis Leakage current Fault detection

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A 1GHz-GBW operational amplifier for DVB-H receivers in 65nm CMOS

A 1GHz-GBW operational amplifier for DVB-H receivers in 65nm...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Heimo Uhrmann Franz Schlogl Kurt Schweiger Horst Zimmermann Institute of Electrical Measurements and Circuit Design University of Technology Vienna Vienna Austria

the offer of information grows rapidly in mobile markets. the DVB-H standard as a part of DVB-T is an important carrier of information to a broad spectrum of consumers. New, cheap and robust receivers have to be developed, especially for handheld devices. We propose a high-speed operational amplifier for a low-pass filter in a direct conversion receiver. In order to integrate the receiver on a system on chip, it is designed in 65 nm low-power CMOS. the operational amplifier is a four-stage feed-forward nested Miller compensated fully differential operational amplifier with an AB output stage. A gain-bandwidth product of 1GHz and a gain of 58 dB is reached. A load capacitance of 5 pF can be driven at a phase margin of 62 deg.

关键词： Operational amplifiers Digital video broadcasting Differential amplifiers Robustness Handheld computers Low pass filters System-on-a-chip Feedforward systems Gain Capacitance

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