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Challenges for test and design for test

Challenges for test and design for test

引用

ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Anton Chichkov On Semiconductor Corporation Oudenaarde Belgium

If test is mentioned normally there are several remarks that have been repeated for the last 20 years. ICs are too fast, patterns are too big, testing is too slow, the test development too costly. Although, the advance of the technology has improved test in general, these statements seems to prevail and sound still valid. One reason is that on every improvement of test strategies there is also improvement of technology and design strategy that keeps the gap open. On the other hand ATE equipment inevitably is build with one generation older technology that keeps the challenge of speed noise and complexity alive. In this presentation the following few challenges for test will be further discussed. How is evolving the gap between test methods tools and equipment on one side and technology, design methodology and design tools on the other? How is evolving the cost of production test equipment and as consequence the cost of test? Is there change in the cost of test development? What about high quality and reliability application testing? And last but not least what about research in the test domain during economic crisis.

关键词： Semiconductor device testing Costs Automatic testing design methodology Application specific integrated circuits Acoustic testing Acoustic noise Noise generators Semiconductor device noise Production

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0.18 µm CMOS UWB LNA with new feedback configuration for optimization low noise, high gain and small area

0.18 µm CMOS UWB LNA with new feedback configuration for op...

引用

ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Y. C. Chang H. L. Kao C. H. Kao C. H. Yang Jeffrey S. Fu Nemai C. Karmakar L. C. Chang Department of Electronic Engineering Chang Gung University Taoyuan Taiwan Department of Accounting Information Takming College Taipei Taiwan Department of Electrical and Computer Systems Engineering Monash University Australia Department of Materials Engineering Ming-Chi University of Technology Taipei Taiwan

In this paper, we present the low noise amplifier using new feedback connection configurations. the UWB LNA is design in 0.18 mum TSMC CMOS technique to achieve high gain, small size and low noise. the LNA achieved 11 dB of average power gain, low 2.87 dB noise figure (NF), -10.9 dB input match, -7 dB return loss, -3 dBm of IIP3 and only 0.54 mm 2 size with 15 mW power consumption.

关键词： Feedback CMOS technology Impedance matching Radio frequency Circuit topology Shunt (electrical) Low-noise amplifiers Energy consumption Broadband amplifiers Ultra wideband technology

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Cognitive self-adaptive computing and communication systems: Test, control and adaptation

Cognitive self-adaptive computing and communication systems:...

引用

ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Abhijit Chatterjee Georgia Institute of Technology Atlanta USA

CMOS technology scaling along with the resulting large variability of circuit performance has made post-silicon circuit and algorithmic level built-in test and adaptation/tuning almost a necessity for deeply scaled technologies. Currently, circuits are designed to tolerate worst-case process corners. In addition, circuits as well as demodulation/signal processing algorithms must be designed for worst case operating conditions (e.g. environmental noise). this forces designers to excessively guard band their circuits while using ldquoaggressiverdquo back-end algorithms to support the end application, resulting in unacceptable power-performance-yield tradeoffs. One way to tackle this problem is to design circuits and relevant signal processing algorithms that are cognitive of their environmental operating conditions and manufacturing process conditions and use this cognition to perform self-adaptation that conserves power while maximizing yield and reliability. Such self-adaptation involves incorporation of built-in test, diagnosis and tuning/adaptation mechanisms into the circuits and systems concerned. A key issue is that of test, diagnosis and tuning of complex circuit and system-level parameters that must be evaluated and traded off against one another during the adaptation process without access to complex external test instrumentation. this talk summarizes recent results obtained in the design of such cognitive computing and communication systems and points to directions for future work in this area.

关键词： Automatic testing System testing Communication system control Control systems Circuit testing Circuit optimization Signal processing algorithms CMOS technology Algorithm design and analysis Built-in self-test

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Self-timed thermal sensing and monitoring of multicore systems

Self-timed thermal sensing and monitoring of multicore syste...

引用

ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Kameswar Rao Vaddina Ethiopia Nigussie Pasi Liljeberg Juha Plosila Department of Information Technology University of Turku Turku Finland

As the number of cores increases thermal challenges increase, thereby degrading the performance and reliability of the system. We approach this challenge with a self-timed thermal monitoring method which is based on the use of thermal sensors. Since leakage currents are sensitive to temperature and increase with scaling, we propose the use of a leakage current based thermal sensing for monitoring purposes. In this work we have implemented a novel thermal sensing circuit in 65 nm CMOS technology, which converts analog temperature information into digital form. We have also proposed a novel thermal sensing and monitoring interconnection network structure based on self-timed signaling, comprising of an encoder/transmitter and decoder/ receiver. We have performed power supply noise, additive noise on sensor input signal and dynamic power supply voltage variation analysis on the thermal sensing circuit and show that it is robust enough under different operating temperatures.

关键词： Monitoring Multicore processing Temperature sensors thermal sensors Leakage current circuits CMOS technology Power supplies Additive noise thermal degradation

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Fast congestion-aware timing-driven placement for island FPGA

Fast congestion-aware timing-driven placement for island FPG...

引用

ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Jinpeng Zhao Qiang Zhou Yici Cai EDA Laboratory Department of Computer Science Tsinghua University Beijing China

A new fast timing-driven placement is presented in this paper, which is partitioning-based method, explicitly considering the congestion for island style FPGAs. the most distinct feature of this approach is that it not only reduces the circuit critical path delay efficiently, but also takes congestion into account. the harmony between partitioning objective and timing improvement goal is kept; moreover, the congestion constraint is added to cost function to improve routability in the meantime. As a result, it avoids the excessive usage of local routing resources while remaining circuit performance much better. the experimental results show our method, FCTP, is very fast. It is able to produce solutions with equal or better routability and up to average 8.19% improvement on performance but only less 1/3 average runtime compared to TVPR [1]. It also achieves much better results than PPFF [7] in terms of timing and congestion with negligible runtime penalty.

关键词： Field programmable gate arrays Delay Runtime Timing Circuit optimization electronic design automation and methodology Cost function Routing Assembly Optimization methods

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Architecture model for approximate palindrome detection

Architecture model for approximate palindrome detection

引用

ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Tomas Martinek Jan Vozenilek Matej Lexa Faculty of Information Technology Brno University of Technology Brno Czech Republic Faculty of Informatics Masaryk University Brno Czech Republic

Understanding the structure and function of DNA sequences represents an important area of research in modern biology. One of the interesting structures occurring in DNA is a palindrome. Biologists believe that palindromes play an important role in regulation of gene activity and other cell processes because they are often observed near promoters, introns and specific untranslated regions. Unfortunately, the time complexity of algorithms for palindrome detection increases when mutations in the form of character insertions, deletions or substitutions are taken into consideration. In recent years, several works have been aimed at acceleration of such algorithms using dedicated circuits capable of potentially large-scale searching. However, widespread use of such circuits is often complicated by varying user task details or the need to use a specific target platform. the objective of this work is therefore to create a model of hardware architecture for approximate palindrome detection and develop a technique for automatic mapping of this model to the target platform without intervention of an experienced designer. the proposed model and the mapping technique are implemented and evaluated on a family of chips with Virtex5 technology.

关键词： DNA Sequences Genetic mutations circuits Hardware Cells (biology) Large-scale systems Computer architecture Bandwidth Information technology

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An on-line testing scheme for repairing purposes in Flash memories

An on-line testing scheme for repairing purposes in Flash me...

引用

ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Olivier Ginez Jean-Michel Portal Hassen Aziza Université de Provence Aix-Marseille 1 Marseilles France

the constant evolution of technologies involves a large amount of problems during and after Flash memory manufacturing. In this context, manufacturers must develop methods and design solutions to improve reliability especially for automotive applications. For this purpose, ECC and BISR are probably the most efficient concepts to enhance memory reliability. However, such techniques are limited to correct errors occurring punctually within a word whereas in memories the stress of peripheral circuit can lead to an entire faulty bit or word line. this phenomenon is referred as Clustering Effect. this work proposes an on-line testing structure for clustering effects according to the word line plan. this test structure allows achieving a test time acceptable and is shown as low cost in term of surface overhead (3 HV transistors, 1 XOR, 1 MUX and 1 DFF). Adding our solution to recent ECC and BISR techniques, spatial or automotive applications could be easily targeted.

关键词： Flash memory Circuit testing Manufacturing Automotive applications design methodology Error correction codes Error correction Stress Circuit faults Costs

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Packet header analysis and field extraction for multigigabit networks

Packet header analysis and field extraction for multigigabit...

引用

ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Petr Kobiersky Jan Korenek Libor Polcak Faculty of Information Technology Brno University of Technology Brno Czech Republic CESNET z.s.p.o. Prague Czech Republic

Packet header analysis and extraction of header fields needs to be performed in all network devices. As network speed is increasing quickly, high speed packet header processing is required. We propose a new architecture of packet header analysis and fields extraction intended for high-speed FPGA-based network applications. the architecture is able to process 20 Gbps network links with less than 12 percent of available resources of Virtex 5 110 FPGA. Moreover, the presented solution can balance between network throughput and consumed hardware resources to fit application needs. the architecture for packet header processing is generated from standard XML protocol scheme and is strongly optimised for resource consumption and speed by an automatic HDL code generator. Our solution also enables to change the set of extracted header fields on-line without FPGA reconfiguration.

关键词： Protocols Field programmable gate arrays throughput Engines Data mining Costs Information technology Performance analysis Hardware design languages Intrusion detection

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Comprehensive bridging fault diagnosis based on the SLAT paradigm

Comprehensive bridging fault diagnosis based on the SLAT par...

引用

ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Y. Benabboud A. Bosio L. Dilillo P. Girard S. Pravossoudovitch A. Virazel L. Bouzaida I. Izaute ST Microelectronics s.r.l. Crolles France Laboratoire dÍnformatique de Robotique et de Microélectronique de Montpellier LIRMM-Université Montpellier II CNRS France

this paper presents a logic diagnosis approach targeting bridging faults. the proposed approach is performed in two phases, (i) a fault localization phase based on the single-location-at-a-time (SLAT) paradigm determining a set of suspects, and (ii) a fault model allocation phase associating a set of fault models to each suspect identified during the first phase. the main advantages of this approach are that the fault localization phase is fault model independent, and that the fault model allocation phase is able to deal at the same time with several bridging fault models leading to either static or dynamic faulty behaviors. Experimental results on full scan circuits show the diagnosis accuracy of the proposed approach in terms of absolute number of suspects. Moreover, a comparison with an industrial reference tool highlights the reliability of our approach.

关键词： Fault diagnosis Circuit faults Dictionaries Circuit simulation Sequential circuits Logic testing Circuit testing Costs Performance evaluation Robots

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On the role of the power supply as an entry for common cause faults—An experimental analysis

On the role of the power supply as an entry for common cause...

引用

ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Peter Tummeltshammer Andreas Steininger Embedded Computing Systems Group University of Technology Vienna Vienna Austria

the principle of duplication and comparison has proven very efficient for error detection in processor cores, since it can be applied as a generic solution for making virtually any type of core fail safe. A weakness of this approach, however, is the potential for common cause faults: Faults affecting both cores in the same way will escape detection. Shared resources and signals are especially prone to such effects. In practice the efforts for providing a redundant power source are often prohibitive, thus rendering the power supply such a shared resource. While a complete failure of the supply voltage can be relatively easily accommodated in a fail safe system, short pulses can have subtle consequences and are therefore much more dangerous. In this paper we will perform an experimental study of the potential of such power supply induced faults to create common cause effects. For this purpose we first study their effects on the operation of a processor core. In particular we will show that, when applied with the most adverse parameters, they tend to cause timing violations in the critical path. In two instances of the same core there is therefore a non-negligible risk of common cause effects. We will quantitatively assess this risk through fault injection experiments into an FPGA based dual core design.

关键词： Power supplies Circuit faults Voltage Delay effects Computer architecture Digital circuits Integrated circuit interconnections Embedded computing Drives Driver circuits

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