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检索条件"任意字段=13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

共 683 条记录，以下是51-60 订阅

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Adaptive Input Normalization for Quantized Neural Networks

Adaptive Input Normalization for Quantized Neural Networks

引用

ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Jan Schmidt Petr Fišer Miroslav Skrbek Dept. of Digital Design CTU in Prague Prague Czech Republic

Neural networks with quantized activation functions cannot adapt the quantization at the input of their first layer. Preprocessing is therefore required to adapt the range of input data to the quantization range. Such preprocessing usually includes an activation-wise linear transformation and is steered by the properties of the training set. We suggest to include the linear transform into the training process. Using the Jet Stream Classification task and an evaluation architecture of three quantized dense layers, we document that it improves accuracy, requires the same resources as standard preprocessing, plays a role in network pruning, and is reasonably stable with respect to initialization.

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PolyAdd: Polynomial Formal Verification of Adder circuits 24

PolyAdd: Polynomial Formal Verification of Adder Circuits

引用

24th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Drechsler, Rolf Univ Bremen Inst Comp Sci D-28359 Bremen Germany

ISBN: (纸本)9781665435956

Only by formal verification approaches functional correctness can be ensured. While for many circuits fast verification is possible, in other cases the approaches fail. In general no efficient algorithms can be given, since the underlying verification problem is NP-complete. In this paper we prove that for different types of adder circuits polynomial verification can be ensured based on BDDs. While it is known that the output functions for addition are polynomially bounded, we show in the following that the entire construction process can be carried out in polynomial time. this is shown for the simple Ripple Carry Adder, but also for fast adders like the Conditional Sum Adder and the Carry Look Ahead Adder. Properties about the adder function are proven and the core principle of polynomial verification is described that can also be extended to other classes of functions and circuit realizations.

关键词： Formal verification

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Prevention and Detection Methods of Systematic Failures in the Implementation of SoC Safety Mechanisms not Covered by Regular Functional Tests 24

Prevention and Detection Methods of Systematic Failures in t...

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24th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Dutey, Denis Martin, Stephane Merlande, Anne Ranjan, Om STMicroelectronics Automot Digital Solut RnD Dept Grenoble France STMicroelectronics Automot Digital Solut RnD Dept Greater Noida India

ISBN: (纸本)9781665435956

Hardware functional safety requirements are covered by verification and validation methods defined by ISO 26262 functional safety standard for automotive electronic systems. the implementation of most functional safety requirements for electronic devices can he covered by typical functional test methods at Register Transfer Level (RTL), complemented by formal proof to ensure that the RTL is equivalent to the netlist and to the physical implementation levels beyond. However, some implementation failures (systematic errors) cannot be detected using this method. this paper reports the cases faced during the development of a complex System-on-Chip for the automotive industry and discusses the verification and implementation checks that were performed to fill this gap.

关键词： Safety Management Safety Analysis design for Safety Verification Validation ISO 26262 V&V Automotive Redundancy Systenzatic failures RTL synthesis ASIL-D

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design and Implementation Strategy of Adaptive Processor-Based systems for Error Resilient and Power-Efficient Operation 24

Design and Implementation Strategy of Adaptive Processor-Bas...

引用

24th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Veleski, Mitko Huebner, Michael Krstic, Milos Kraemer, Rolf BTU Cottbus Senftenberg Chair Comp Engn Cottbus Germany IHP Leibniz Inst Innovat Mikroelekt Frankfurt Oder Germany Univ Potsdam Potsdam Germany

ISBN: (纸本)9781665435956

the contemporary computing systems are facing two major challenges: excessive power consumption and susceptibility to faults. In order to take advantage of techniques that efficiently address these challenges, the classic ASIC design flow requires some modifications. In this paper, we present a simple and convenient strategy for design and implementation of processor-based systems using highly configurable, cross-layer framework that encompasses techniques such as Adaptive Voltage and Frequency Scaling (AVFS) and Triple Modular Redundancy (TMR). the proposed strategy augments the conventional design flow with two additional steps to integrate the framework's hardware building blocks into the system. Such system is then able to dynamically switch between low power and error resilient operation modes according to the current requirements. By following the proposed strategy, we were able to implement processor-based system that significantly reduces the power consumption / increases the soft error resilience while preserving the performance at negligible area overhead of less than 1%.

关键词： Electric power utilization

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Controllability-Based Circuit Similarity Estimation

Controllability-Based Circuit Similarity Estimation

引用

ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Michal Žáček Petr Fišer Department of Digital Design Faculty of Information Technology Czech Technical University in Prague Prague Czech Republic

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

Assessing the structural similarity of different implementations of logic functions is of importance in many areas of digital design, such as iterative resynthesis, engineering change order (ECO) based design, design of reliable redundant systems (duplex, TMR), etc. In general, numerous metrics exist that describe such similarity, mostly based on its intended application. In this paper, we introduce a novel metric based on a calculation of the functional equivalence of subcircuits. As this approach requires repeated calls of time-consuming functional equivalence checking, we propose a linear-time approximation of this method based on signal controllability calculation. these two approaches are compared to the state-of-the-art fault detection-based design diversity estimation technique and applied to assess the fault-security capabilities of duplex systems.

关键词： Measurement Fault detection Estimation Reliability engineering Logic functions Electrical fault detection Controllability Iterative methods Integrated circuit reliability electronic circuits

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A Comparison of Logic Extraction Methods in Hardware-Translated Neural Networks

A Comparison of Logic Extraction Methods in Hardware-Transla...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Jan Schmidt Petr Fišer Miroslav Skrbek Dept. of Digital Design CTU in Prague Prague Czech Republic

Small quantized neural networks with strong requirements on throughput and latency can be translated into logic circuits and synthesized by logic design tools. With networks having no state (memory), the circuits are combinational. To capture the function of the network (or a part of it) as a logic function, two approaches have been taken. the first one observes the inputs and outputs, while the network predicts a training set, and uses them directly as specification. the response to activation values that have not occurred in the training set remains unspecified. the other approach uses a complete set of activation values at the input of the examined part. We measured accuracy, the influence of logic minimization, and their impact on the final synthesized circuit on dense neural networks in different stages of low-magnitude pruning on the MNIST and JSC datasets. the results show that the first method can be used for functions with fan-in below 10–12 while not working against generalization. We also document the quantitative changes in quantized networks.

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the Impact of Well-Edge Proximity Effect on PMOS threshold Voltage in Various Submicron CMOS Technologies

The Impact of Well-Edge Proximity Effect on PMOS Threshold V...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Marika Grochowska Witold A. Pleskacz Cadence Design Systems Warsaw Poland Warsaw University of Technology Institute of Microelectronics & Optoelectronics Warsaw Poland

This paper explains the background of the well-edge proximity effect (WPE) and sums up its impact on pMOS threshold voltage $(V_{th})$ in the following CMOS technologies: 65nm (bulk), 40nm (bulk) from two different vendors, 28nm (bulk and FDSOI) and 16nm (FinFET). The results clearly show that WPE cannot be ignored during layout design for any of presented technology. Fortunately, the effect of well-edge proximity is essential at 1 μm or shorter distances. At longer distances its impact decreases almost to zero. In 40nm technology it can change threshold voltage even by 33 % for IO devices while at 16nm the change will be just 1.87%. Although the technologies are varied in transistor length and process of fabrication the WPE effect remains present.

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EKV MOS Transistor Model For Ultra Low-Voltage Bulk-Driven IC design 24

EKV MOS Transistor Model For Ultra Low-Voltage Bulk-Driven I...

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24th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Nagy, Lukas Arbet, Daniel Kovac, Martin Potocny, Miroslav Sovcik, Michal Stopjakova, Viera Slovak Univ Technol Bratislava Fac Elect Engn & Informat Technol Inst Elect & Photon Bratislava Slovakia

ISBN: (纸本)9781665435956

the paper addresses a development and evaluation of well-known EKV MOS transistor model with focus on the ultra low-voltage / ultra low-power analog IC design employing rather "exotic" bulk-driven technique. the presented contribution can be viewed as an extension of already established compact simulation model with modifications to the original parameter extraction flow. the article contains a brief description of EKV model fundamentals, a novel parameter extraction flow and most importantly, the comparison of developed EKV model with the foundry-provided BSIM model (v3.3) and the experimental measurement data obtained from prototype chip samples fabricated in 130 nm CMOS technology.

关键词： Bulk-Driven Ultra Low-Voltage Low-Power EKV Model Analog IC design

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Analysis of State Corruption caused by Permanent Faults in WCHB-based Quasi Delay-Insensitive Pipelines 24

Analysis of State Corruption caused by Permanent Faults in W...

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24th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： El Shehaby, Raghda Steininger, Andreas TU Wien Inst Comp Engn Vienna Austria

ISBN: (纸本)9781665435956

Quasi delay-insensitive asynchronous circuits have the appealing property of stopping further operation in case of a permanent fault. this fail-stop behavior makes them attractive for on-line repair: after removal of the permanent fault, the circuit can, ideally, continue operating without the need for state recovery. However, it has been shown that in certain cases the state may get corrupted before the operation actually stops. In this paper we use the example of a weak-conditioned half-buffer template to investigate more closely which situations can lead to such state corruption. We explore implementation variants like double completion detection to mitigate that undesired effect. Based on extensive gate-level simulation experiments we quantify the probability for state corruption seen in the different circuits and identify the relevant dependences. As it turns out, the proposed extensions can reduce, but not completely eliminate, the risk of state corruption. At the same time detection of illegal code words promises to have great potential for countermeasures.

关键词： permanent faults QDI circuits WCHB fault injection

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Logic Resynthesis of Majority-Based circuits by Top-Down Decomposition 24

Logic Resynthesis of Majority-Based Circuits by Top-Down Dec...

引用

24th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Lee, Siang-Yun Riener, Heinz De Micheli, Giovanni Ecole Polytech Fed Lausanne Integrated Syst Lab Lausanne Switzerland

ISBN: (纸本)9781665435956

Logic resynthesis is the problem of ding a dependency function to re-express a given Boolean function in terms of a given set of divisor functions. In this paper, we study logic resynthesis of majority-based circuits, which is motivated by the increasing interest in majority logic optimization due to the recent. development of beyond-CMOS technologies. To meet the need for an efficient majority resynthesis heuristic, we propose a top-down decomposition algorithm, whose complexity is linear to both n and era, where n is the number of divisors and m is the number of majority operations in the dependency function. We evaluate the resynthesis algorithms by using them in a resubstitution run applied on the EPFL benchmark suite. the experimental results show that, comparing to the state-of-the-art enumeration algorithm whose complexity grows exponentially with m, using the proposed decomposition algorithm leads to 1.5% more circuit size reduction by lifting the limitation on m, within comparable runtime.

关键词： Logic synthesis combinational circuit peephole optimization majority-inverter graph Boolean resubstitution

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