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检索条件"任意字段=13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

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Effective BIST for crosstalk faults in interconnects

Effective BIST for crosstalk faults in interconnects

引用

ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Tomasz Rudnicki Tomasz Garbolino Krzysztof Gucwa Andrzej Hlawiczka Institute of Electronics Silesian University of Technology Gliwice Poland

the paper is devoted to a test-per-clock method of an at-speed testing of crosstalk faults in long interconnects between cores in systems-on-a-Chip. A linear feedback shift register (LFSR) composed of 2n flip-flops and implementing primitive polynomial was used as a test pattern generator (TPG) for an interconnect network comprised of n nets. In our approach every second output of the LFSR is connected to the interconnect network under test (INUT). Simulation-based experiments were carried out to verify effectiveness of vector sequences produced by the proposed TPG in detection of crosstalk faults provoked at victim net by simultaneous occurrence of rising (falling) edges 01(10) at k aggressor lines. Crosstalk faults causing occurrence of a positive (negative) glitch at a victim line having constant value 00(11) as well as the ones that make the edge delayed with an opposite direction 10(01) at a victim line were taken into consideration. Experimental results demonstrated that for n e {8,12,16,20,24,28,32} and k<

关键词： Built-in self-test Crosstalk Integrated circuit interconnections Circuit faults Fault detection System-on-a-chip Frequency electronic equipment testing Circuit testing System testing

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Improve clock gating through power-optimal enable function selection

Improve clock gating through power-optimal enable function s...

引用

ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Juanjuan Chen Xing Wei Yunjian Jiang Qiang Zhou Department of Computer Science and Technology Tsinghua University Beijing China Magma Design-Automation Inc. USA

Clock gating technology can reduce the consumption of clock signals' switching power of flip-flops. the clock gate enable functions can be identified by Boolean analysis of the logic inputs for all flip flops. However, the enable functions of clock gate can be further simplified, and the average number of flip flops driven by enable functions can be improved. In this way, the circuit area can be reduced; therefore, the clock gating can be improved and power saving can be achieved. this paper presents a technique for improving clock gating by optimizing the enable functions. the problem of improving clock gating is formulated as finding the optimal set of enable functions in the shared logic cone that leads to best power reduction on flip flops. First, enable functions are identified by random simulation and SAT. then the optimal set of enable functions is found with partition method. this paper demonstrates the effectiveness of the approach through testing on MCNC benchmarks and industrial circuits. the experimental results show that the algorithm will get as much power saving as 3 times of that of the original clock gating circuits, and all benchmarks can run in tens of seconds.

关键词： Clocks Flip-flops Power dissipation Circuit synthesis Circuit testing Benchmark testing Feedback loop Energy consumption Logic testing Computer science

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An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs

An enhanced FPGA-based low-cost tester platform exploiting e...

引用

ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： L. Ciganda F. Abate P. Bernardi M. Bruno M. Sonza Reorda Universidad de la Republica Montevideo Uruguay Politecnico di Torino Torino Italy

Reducing the cost of test (in particular by reducing its duration and the cost of the required ATE) is a common goal which has largely been pursued in the past, mainly by introducing suitable on chip design for Testability (DfT) circuitry. Today, the increasing popularity of sophisticated DfT architectures and the parallel emergence of new ATE families allow the identification of innovative solutions effectively facing that goal. In this paper we face the increasingly common situation of SoCs adopting the ieee 1149.1 and 1500 standards for the test of the internal cores, and explore the idea of storing the test program on the tester in a compressed form, and decompressing it on-the-fly during test application. this paper proposes an improved version of an data compression/decompression technique which is well suited for reducing the size of test programs stored on the tester; this technique is particularly effective for very long sequential test vectors generated to test SoCs by means of low-cost test procedures; thus, the paper outlines the characteristics of an FPGA-based low-cost tester platform that takes advantage of the described compression schema. the effectiveness of the proposed methodology was demonstrated by practically testing some SoCs equipped with suitable DfT for supporting low-cost testing resorting to a low-cost tester implementing the proposed architecture and the compression/decompression technique.

关键词： Test data compression Circuit testing Sequential analysis Automatic testing design for testability Built-in self-test Costs Software testing Data compression Frequency

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All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter tolerance

All digital baseband 50 Mbps data recovery using 5× oversam...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Sanad Bushnaq Toru Nakura Makoto Ikeda Kunihiro Asada Electronics Engineering University of Tokyo Japan VLSI Design and Education Center University of Tokyo Japan Electronics Engineering VLSI Design and Education Center University of Tokyo Japan

In this paper, an all digital baseband data recovery algorithm using oversampling technique is presented. Our algorithm uses 5times clock to sample incoming data once around the middle. Sampling occurs exactly on the third clock after a data edge. If no data edge sensed, sampling occurs after five clocks from the previous sample. the system is designed to receive 50 Mbps data bit rate and uses a 250 MHz local clock to do the oversampling process. After injecting the clock with jitter at various magnitudes and frequencies, the design showed around 0.9 data Unit Interval (UI data ) jitter tolerance at frequencies higher than 25 MHz, in addition to a low Bit Error Rate (BER < 10 -11 ). the setup is implemented on an Altera Stratix II GX Field Programmable Gate Array (FPGA) while Agilent 81250 parallel Bit Error Ratio Tester (parBERT) is used to measure BER using Pseudo Random Bit Sequences (PRBS). Using 0.18 mum CMOS process, the design consumes as low power as 5 muW, which makes it effective for low power applications such as wireless image sensor nodes.

关键词： Baseband Clocks Jitter Bit error rate Sampling methods Frequency Field programmable gate arrays Bit rate Testing CMOS process

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design and implementation of a socket with low standby power

Design and implementation of a socket with low standby power

引用

ieee International symposium on Consumer electronics (ISCE)

作者： Cheng-Hung Tsai Ying-Wen Bai Hao-Yuan Wang Ming-Bo Lin Department of Electronic Engineering National Taiwan University of Science and Technology Taipei Taiwan Department of Electronic Engineering Fu Jen Catholic University Taipei Taiwan

Turned-off electric home appliances generally they still require standby power when they are plugged in. In this paper we present a way to reduce the standby power of a socket. Our socket supplies the appliances with power when the user turns them on. When the user turns them off, our socket shuts the electric power off and reduces the standby power to zero. Our design uses an MCU which receives signals from a PIR sensor which detects the user when approaching the socket and the appliances. A power detector provides an MCU to control the SSR On/Off when used as an appliance switch for shutting off the standby power. the components we use are very inexpensive and consume less than 0.4 W. the MCU monitoring program provides both automatic detection of the user by the PIR sensor and detection of power consumption.

关键词： Sockets Home appliances Energy consumption Switches Microcontrollers Power engineering and energy Protection circuits Low voltage Consumer electronics

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A peak current and power pad count reduction tool for system-level IC designers

A peak current and power pad count reduction tool for system...

引用

ieee International symposium on Consumer electronics (ISCE)

作者： Tsung-Yi Wu Tzi-Wei Kao Shi-Yi Huang Tai-Lun Li How-Rern Lin Department of Electronic Engineering National Changhua University of Education Changhua Taiwan Department of Computer Science and Information Engineering Da-Yeh University Changhua Taiwan

In a typical synchronous circuit system, a large peak current occurs near the time of an active clock edge because of the aggregate switching of a large number of transistors. A huge peak current causes circuit designers to increase the power pad number for preventing voltage drop problem. the number of aggregate switching gates can be cut in half at most if the circuit system can use a clock scheme of mixed positive and negative triggering edges rather than one of pure positive (negative) triggering edges. In this paper, we propose a software tool that can assign either a rising triggering edge or a falling triggering edge to each clock of each block of a given system-level design. the goal of the clock-triggering-edge assignment is to reduce the peak current of the design. Experimental results show that our tool can reduce the peak current up to 45.3% and reduce the power pad count up to 40.0%.

关键词： Clocks Flip-flops Voltage Logic design Switching circuits Delay design engineering Power engineering and energy Aggregates Software tools

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Mixed-signal DFT for fully testable ASIC

Mixed-signal DFT for fully testable ASIC

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11th ieee International Workshop on design and diagnostics of electronic circuits and systems

作者： Reznicek, Frantisek AMI Semicond Czech SRO Brno 61900 Czech Republic

ISBN: (纸本)9781424422760

An efficient mixed-signal design strategy for test insertion standardization. the mixed-signal DFT (design For Test) strategy is built on three main linchpins: DFT and other design rules, DFT design structures and finally design to test interactions. Such a design strategy improves the overall device fault coverage which leads to minimal device failure rate on the customer side. this poster article explains first the design strategy in detail and finally highlights the reached results.

关键词： Application specific integrated circuits

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Excitation optimization in fault diagnosis of analog electronic circuits

Excitation optimization in fault diagnosis of analog electro...

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11th ieee International Workshop on design and diagnostics of electronic circuits and systems

作者： Chruszczyk, L. Rutkowski, J. Silesian Tech Univ Inst Elect Gliwice Poland

ISBN: (纸本)9781424422760

this article describes optimization of excitation signal for purpose of fault diagnosis. the goal is to enhance efficiency of faults detection in analog electronic circuits. the method has been verified on cases with single hard (catastrophic) and soft (parametric) faults. Further enhancement of fault detection efficiency has been achieved with additional feature extraction by means of wavelet transform. Obtained results have been compared with diagnosis using step function excitation and diagnosis without feature extraction.

关键词： Fault detection

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Implementation of dynamically reconfigurable test architecture for FPGA circuits

Implementation of dynamically reconfigurable test architectu...

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11th ieee International Workshop on design and diagnostics of electronic circuits and systems

作者： Rozkovec, Martin Tech Univ Inst Informat Technol & Elect Liberec Czech Republic

ISBN: (纸本)9781424422760

this paper presents the BIST architecture for SOPC circuits. DyRespin reuses scan chains in embedded cores for decompression of highly compressed test vectors. the test access mechanism (TAM) for scan chain connections is implemented as a reconfigurable module. We reuse the switching logic in the interconnection matrix in order to save logic resources. For circuits with higher number of scan chains, the reconfigurable TAM is much more effective than the multiplexer based TAM, comparing usage of the logic resources and clock speeds.

关键词： Timing circuits

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design of erasure codes for digital multimedia transmitting

Design of erasure codes for digital multimedia transmitting

引用

11th ieee International Workshop on design and diagnostics of electronic circuits and systems

作者： Shinkarenko, K. V. Vlcek, K. Tomas Bata Univ Nad Stranemi 4511 Zlin 76001 Czech Republic

ISBN: (纸本)9781424422760

A new approach for erasure codes design with regards to digital multimedia specificity is introduced. the experimental results on coding effectiveness are obtained. Comparison with reference to LT (Luby Transform) codes is performed. the proposed erasure codes allow to achieve more robust decoding for high packet-loss ratios. the designed encoding algorithm is well-fit for hardware parallel processing.

关键词： Codes (symbols)

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