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检索条件"任意字段=13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

共 683 条记录，以下是601-610 订阅

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IP-based systematic design of power- and matching-limited circuits

IP-based systematic design of power- and matching-limited ci...

引用

11th ieee International Workshop on design and diagnostics of electronic circuits and systems

作者： Smola, David Pantucek, Ludek AMI Semicond Czech Brno 61900 Czech Republic

ISBN: (纸本)9781424422760

In this paper we present a systematic top-down methodology for designing power-limited and matching-limited circuits with a help of IP database. the presented methodology is a helpful tool for the circuit performance optimization and for the design time shortening. the approach is illustrated on a design of a measuring channel front-end, which senses an external high-voltage signal. the circuit is a signal conditioning front-end for an A/D converter input where the critical design parameters are the power consumption, the matching and the transient response and last but not least the design time. the circuit was implemented in an ASIC and manufactured in 0.35 mu m high-voltage CMOS technology.

关键词： Timing circuits

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A new design technique for weakly indicating function blocks

A new design technique for weakly indicating function blocks

引用

11th ieee International Workshop on design and diagnostics of electronic circuits and systems

作者： Balasubramanian, P. Edwards, D. A. Univ Manchester Sch Comp Sci Manchester M13 9PL Lancs England

ISBN: (纸本)9781424422760

this paper presents a novel technique for gate-level design of combinatorial logic as weakly indicating function blocks. the input state space associated with a function block expands exponentially with a gradual increase in the number of inputs. As a result, large area overhead would incur for an asynchronous realization. Hence, a novel design methodology for realizing combinational logic as a function block is developed under the discipline of quasi-delay-insensitivity with four-phase handshaking and dual-rail encoding, whilst trying to mitigate the area overhead. the focus is on design adhering to the weakly indicating timing regime. Based on analysis with some combinational benchmarks and widely used logic circuit functionality, the proposed method is found to enable compact realizations and appears to be promising for weakly indicating function block design comprising many inputs and outputs.

关键词： Computer circuits

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Gain reduction by gate-leakage currents in regulated cascodes

Gain reduction by gate-leakage currents in regulated cascode...

引用

11th ieee International Workshop on design and diagnostics of electronic circuits and systems

作者： Schloegl, F. Schneider-Hornstein, K. Zimmermann, H. Vienna Univ Technol Inst Elect Measurements & Circuit Design Gusshausstr 25-354 A-1040 Vienna Austria

ISBN: (纸本)9781424422760

the gain reduction of nanometer-size MOS transistors due to the high output conductance of the devices is already discussed in the literature. this paper discusses an additional issue which leads to further gain reduction - the gate-leakage current. On the basis of the example of a regulated cascode in 130nm CMOS and in 65nm CMOS it is estimated that this shrinking step decreases the gain due to gate-leakage current by about 30 to 40dB.

关键词： Leakage currents

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the influence of global parametric faults on analogue electronic circuits time domain response features

The influence of global parametric faults on analogue electr...

引用

11th ieee International Workshop on design and diagnostics of electronic circuits and systems

作者： Jantos, P. Grzechca, D. Golonek, T. Rutkowski, J. Silesian Tech Univ Gliwice Poland

ISBN: (纸本)9781424422760

this paper presents an analysis of an influence of global parametric faults (GPF) on analogue integrated circuits (AIC) time domain (TD) response features, such as overshoot, delay time, rise time, maxima and minima, first differential maxima and minima. the novel approach is the analysis of relations and superrelations between features which are discussed in details. the presented results should increase testability and diagnosability of the global parametric faults on a production line of analogue and mixed electronic circuits. the recently observed AIC faults belong to parametric ones and are caused by technological process. GPF influence on aforementioned features is presented with the use of an exemplary circuit. A research presented in this paper may be used as an introduction to a Fault Driven Test (FDT) diagnosis with the use of Simulation Before Test (SBT) methods.

关键词： Analog integrated circuits

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Experimental analog circuit for parametric test methods efficiency evaluation

Experimental analog circuit for parametric test methods effi...

引用

11th ieee International Workshop on design and diagnostics of electronic circuits and systems

作者： Brenkus, J. Stopjakova, V. Mihalov, J. Slovak Tech Univ Dept Microelect Bratislava 81219 Slovakia

ISBN: (纸本)9781424422760

An experimental analog design for parametric test methods efficiency evaluation is presented. the circuit is implemented in a standard 0.35 mu m CMOS process by AMS. the circuit under test (CUT) is a two-stage operational amplifier with implemented addressable faults. the control of the overall circuit is ensured by a 7-bit shift register. For higher loading capability a buffer is connected to the output. To preserve the possibility of voltage ramping, the CUT has a separated supply rail. the CUT can be also connected to a feedback network integrated on the chip, and thus, turned into an oscillator.

关键词： Analog circuits

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three subthreshold flip-flop cells characterized in 90 nm and 65 nm CMOS technology

Three subthreshold flip-flop cells characterized in 90 nm an...

引用

11th ieee International Workshop on design and diagnostics of electronic circuits and systems

作者： Alstad, Havard Pedersen Aunet, Snorre Univ Oslo Dept Informat N-0316 Oslo Norway

ISBN: (纸本)9781424422760

this paper examines three different flip-flop designs in subthreshold operation. All flip-flops are simulated in a 65 nm and 90 nm process with a supply voltage ranging from 125 mV to 1 V. Process variations are examined at different process corners. Successful operations of a PowerPC 603 flip-flop at all process corners with a supply voltage down to 125 mV is shown at 65 nm. the best PDP and EDP numbers of flip-flops design at V-DD = 200 mV in this paper are 53.6 aJ and 0.88 yJs, respectively.

关键词： Flip flop circuits

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Low-voltage low-power highly linear down-sampling mixer in 65nm digital CMOS technology

Low-voltage low-power highly linear down-sampling mixer in 6...

引用

11th ieee International Workshop on design and diagnostics of electronic circuits and systems

作者： Schweiger, Kurt Zimmermann, Horst Vienna Univ Technol Inst Elect Measurement & Circuit Design A-1040 Vienna Austria

ISBN: (纸本)9781424422760

A highly linear down-conversion mixer in a 65nm digital CMOS technology is presented. the mixer was fabricated in a tripple-well process which allows to use the bulk of NMOS transistors as inputs. In contrary to other works not the gate but the bulk connector is used for the input signal. A high IIP3 of +18dBm was achieved with a power consumption of only 0.67mW from a 1.2V supply voltage. the mixer has a measured 1dB compression point of +7dBm. the input signal bandwidth lies beyond 2GHz.

关键词： Mixers (machinery)

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design and simulation of runtime reconfigurable systems

Design and simulation of runtime reconfigurable systems

引用

11th ieee International Workshop on design and diagnostics of electronic circuits and systems

作者： Pionteck, thilo Albrecht, Carsten Koch, Roman Brix, Torben Maehle, Erik Med Univ Lubeck Inst Comp Engn D-23538 Lubeck Germany

ISBN: (纸本)9781424422760

this paper presents an architectural framework and simulation model for tile-based runtime reconfigurable systems. the framework accounts for all hardware limitations of actual FPGA devices and is based on the division of the reconfigurable system partition into a set of small tiles. these tiles can either be exchanged individually at runtime or can be grouped to larger tiles and be exchanged as a whole. the adaptive tile size allows the realization of hardware modules of varying sizes. For easing the system design process a SystemC simulation methodology at a high abstraction level is presented which provides support for all architectural features of the hardware framework. In particular, the capability of simulating runtime reconfigurable systems is supported by the simulation methodology without modifying the SystemC kernel. the applicability of the architectural framework and of the simulation model is demonstrated by means of an example.

关键词： systems analysis

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Ad-hoc translations to close Verilog semantics gap

Ad-hoc translations to close Verilog semantics gap

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11th ieee International Workshop on design and diagnostics of electronic circuits and systems

作者： Haufe, Christian Rogin, Frank AMD Saxony LLC & Co KG Dresden Design Ctr Dresden Germany Fraunhofer Inst Integrated Circuits Div Design Automat Dresden Germany

ISBN: (纸本)9781424422760

this paper describes rules to transform Verilog HDL source code in order to propagate X-values on RTL models in a more realistic way, and to check for potential differences of RTL simulation results against expected silicon implementation behavior. By running X-propagation simulations in parallel to usual RTL simulation and debugging, RTL design bugs previously detected in gate-level simulations can be detected earlier now. A prototypical tool automatically implements the proposed transformation rules. Experimental results on two industrial hardware designs validate the usefulness of our approach and justify its application in everyday use.

关键词： Semantics

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Continuous-time common-mode feedback circuit for applications with large output swing and high output impedance

Continuous-time common-mode feedback circuit for application...

引用

11th ieee International Workshop on design and diagnostics of electronic circuits and systems

作者： Yan, Weixun Zimmermann, Horst Vienna Univ Technol Inst Elect Measurements & Circuit Design A-1040 Vienna Austria

ISBN: (纸本)9781424422760

Motivated by the fact that no existing common mode feedback block (CMFB) can work for the systems characterized with both high output impedance and large output swing, a new CMFB topology is introduced in this paper to accomplish this task. Various types of CMFB are studied, analyzed and simulated. Compared with other CMFBs, the proposed CMFB obtains the widest linear input range, smallest output common-mode level error, largest (full) output swing and has no interference to the system output impedance. All these properties entitle the presented CMFB circuit to suit all types of fully differential systems, especially for systems which require both high output impedance and large signal output swing.

关键词： Continuous time systems

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