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检索条件"任意字段=13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

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Built-In Current monitor for I_DDQ testing in CMOS 90 nm technology

Built-In Current monitor for I<sub>DDQ</sub> testing in CMOS...

引用

11th ieee International Workshop on design and diagnostics of electronic circuits and systems

作者： Beresinski, Marcin J. Borejko, Tomasz Pleskacz, Witold A. Stopjakova, Viera Warsaw Univ Technol Inst Microelect & Optoelect Ul Koszykowa 7 PL-00662 Warsaw Poland Slovak Univ Technol Bratislava Dept Microelect Bratislava 81219 Slovakia Twinteq P-04041 Warsaw Poland

ISBN: (纸本)9781424422760

In this paper, a Built-In Current (BIC) monitor for testing low-voltage digital CMOS circuits is presented. the monitor is designated for typical I-DDQ testing as well as for characterization of supply current values for different test vectors. Voltage drop across the monitor during measurement and the switching phase are minimized. A wide range of currents is supported. Abilities and limitations of the BIC monitor were verified through simulations. Results of post layout simulations are presented as well. the design was implemented in UMC CMOS 90 nm technology.

关键词： CMOS integrated circuits

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A partial scan based test generation for asynchronous circuits

A partial scan based test generation for asynchronous circui...

引用

11th ieee International Workshop on design and diagnostics of electronic circuits and systems

作者： Vasudevan, D. P. Efthymiou, A. Univ Edinburgh ICSA Sch Informat Edinburgh EH8 9YL Midlothian Scotland

ISBN: (纸本)9781424422760

Test Generation for asynchronous circuit is a hard problem mainly due to the absence of a global clock. Full scan design based test generation of asynchronous circuits seems to be feasible but at an expense of large area overhead. Partial scan should be a better option with lower area overhead but there is no known systematic way of selecting which asynchronous state-holding elements to scan. this paper presents a partial scan and automatic test generation methodology based on a novel adaptation of BALLAST for asynchronous circuits and time frame unrolling. Balanced structures are used to guide the selection of the state-holding elements that will be scanned. A cyclic to acyclic conversion of the input circuit is used to create a combinational circuit for which test patterns are easily generated using well known methods. these test patterns are then used to test the original circuit. Fault coverage and area overhead results of this method are obtained and analyzed with full scan and other methods.

关键词： Timing circuits

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A resistorless voltage reference source for 90 nm CMOS technology with low sensitivity to process and temperature variations

A resistorless voltage reference source for 90 nm CMOS techn...

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11th ieee International Workshop on design and diagnostics of electronic circuits and systems

作者： Borejko, Tomasz Pleskacz, Witold A. Warsaw Univ Technol Inst Microelect & Optoelect PL-00662 Warsaw Poland

ISBN: (纸本)9781424422760

A new compact low power voltage reference source for wireless and embedded applications is described. the reference voltage source has been designed in a mixed-signal UMC 90 nm CMOS process using subthreshold characteristics for generating a constant voltage of 423 mV at supply voltages front 1.1 V to 3.3 V with total current consumption 270 nA. the proposed circuit occupies 0.001 mm(2) chip area and achieves less than 110 ppm/degrees C for all process corners and temperature variation from -40 degrees C to 125 degrees C. the power supply rejection ratio without any filtering capacitor at 100 Hz and 10 MHz is lower than -50 dB and -30 dB, respectively. the equivalent output voltage noise in the bandwidth from I Hz to 10 MHz reaches 218 mu V-RMS.

关键词： CMOS integrated circuits

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Improving fault tolerance by using reconfigurable asynchronous circuits

Improving fault tolerance by using reconfigurable asynchrono...

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11th ieee International Workshop on design and diagnostics of electronic circuits and systems

作者： Friesenbichler, Werner Panhofer, thomas Delvai, Martin Austrian Aerosp GmbH Stachegasse 16 A-1120 Vienna Austria Vienna Univ Technol Embedded Comp Syst Grp A-1040 Vienna Austria

ISBN: (纸本)9781424422760

To achieve fault tolerance several tasks have to be performed, from fault detection up to recovery procedures. Sophisticated methods for each sub-task were and are still developed, but rarely a complete solution is proposed on circuit level. this paper fills the gap by proposing a concept that combines all required steps to implement fault tolerant digital circuits. the approach is based on asynchronous Four-State Logic (FSL) logic, which belongs to the family of Quasi Delay Insensitive (QDI) circuits. Contrary to conventional approaches, using synchronous logic plus additional hardware and/or software to achieve fault tolerance, we use the inherent properties of FSL for fault detection, fault localization and fault recovery. Only deadlock detection and error mitigation require an enhancement of the conventional FSL design. For this purpose, a monitoring unit has to he added and self-healing cells were developed that can be handled as conventional logic within the design flow. the feasibility of the approach is verified by a first prototype implementation of a fault tolerant adder circuit.

关键词： Fault tolerance

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design of Time-to-Digital converter output interface

Design of Time-to-Digital converter output interface

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11th ieee International Workshop on design and diagnostics of electronic circuits and systems

作者： Miskowicz, Marek AGH Univ Sci & Technol Dept Elect PL-30059 Krakow Poland

ISBN: (纸本)9781424422760

A design of Time-to-Digital converter output interface for ADCs with asynchronous Sigma-Delta modulation is presented in details in the paper. the concept of the digital interface with double data buffering and asynchronous serial link is carefully explained on the basis of the schematics of particular functional blocks. the TDC design has been optimized in terms of minimizing the power consumption.

关键词： Counting circuits Delta-sigma modulation Quantization Variable speed drives Computer buffers Clocks Buffer storage Sampling methods Flip-flops design optimization

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Foreword

Foreword

引用

ieee European Test symposium (ETS)

Presents the introductory welcome message from the conference proceedings.

关键词： System testing Circuit testing Semiconductor device testing Power system reliability electronic equipment testing Semiconductor device reliability Europe circuits and systems Reliability engineering design engineering

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Controllable Local Clock Signal Generator for Deep Submicron GALS Architectures

Controllable Local Clock Signal Generator for Deep Submicron...

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11th International Workshop on design and diagnostics of electronic circuits and systems (DDECS)

作者： Artur L. Sobczyk Arkadiusz W. Luczyk Witold A. Pleskacz Institute of Microelectronics and Optoelectronics Warsaw University of Technology Warsaw Poland

In the paper a local clock signal generator is presented. the structure was designed in regard to use it in GALS (Globally Asynchronous Locally Synchronous) architectures. the circuit was implemented in UMC (United Microelectronics Corporation) 90 nm CMOS technology. Performed post-layout electrical simulations shown that generated frequency can be efficiently controlled in different working conditions with relative error not grater than 13%.

关键词： Clocks Signal generators Power dissipation circuits Signal design Microelectronics CMOS technology Energy consumption Frequency synchronization Process design

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the Role of Test in circuits Built with Unreliable Components

The Role of Test in Circuits Built with Unreliable Component...

引用

ieee European Test symposium (ETS)

作者： Antonio Rubio Telecommunication Engineering Faculty Technical University of Catalonia (UPC) Barcelona

the talk will reconsider the role of the test in new emerging device circuits for CMOS Terascale and further technologies where a high level of redundancy will be present. As far as we are getting close to ultimate CMOS and ulterior new emerging nano-devices technologies the indication made by J. von Neumann in 1950 that errors had to be viewed not as an extraneous accident but as an essential part of the process under consideration caused by natural phenomena is becoming a real fact. It is well accepted that at the same time electronic technology is going into the deep nanoscale the device reliability decreases rapidly. For such future technologies internal electromagnetic coupling or just thermal noise as well as permanent manufacturing defects will cause a loss of reliability and introduce an inherent error probabilistic factor to every component of the system. these deviations motivate new design paradigms. Many of these deviations will be transient in nature, at the same time current computer architecture approaches are reaching their practical limits. In order to build reliable electronics it will be necessary to include fault and defect tolerant schemes through the introduction of massive redundancy. Within this change of scenario, in comparison to conventional deterministic logic circuits these emerging technologies have to face new design and test strategies in order to give support to this probabilistic behavior logic.

关键词： Circuit testing CMOS technology Redundancy Logic circuits Logic testing CMOS process Accidents Nanoscale devices Electromagnetic coupling Rapid thermal processing

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A 60-GHz Fully-Integrated Doherty Power Amplifier Based on 0.13-μm CMOS Process

A 60-GHz Fully-Integrated Doherty Power Amplifier Based on 0...

引用

Program Comprehension (IWPC 2005), 13th International Workshop on;Atlanta,GA,USA

作者： Byron Wicks Efstratios Skafidas Rob Evans National ICT Australia Department of Electrical and Electronic Engineering University of Melbourne Parkville VIC Australia

A sixty-gigahertz (60-GHz) Doherty power amplifier (PA) has been designed and implemented on 0.13 μm RF-CMOS for use in an integrated 60-GHz transceiver. the fully-integrated design implements the main and auxiliary amplifiers, matching networks, and input and output transmission line networks on-chip. the prototype operating from a 1.6-V supply exhibits an output referred P{sub}(1dB) of 7.0 dB, a P{sub}(SAT) of +7.8 dBm, with peak power gain of 13.5 dB, a 3-dB bandwidth of 6.7 GHz, and 3.0% PAE. the die area is 1.8mm{sup}2. this amplifier achieves the highest reported figure of merit for power amplifiers of any published millimeter-wave PA on CMOS.

关键词： CMOS millimeter wave integrated circuits Doherty amplifier Millimeter wave amplifiers Power amplifiers

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Flip-flops and scan-path elements for nanoelectronics

Flip-flops and scan-path elements for nanoelectronics

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10th ieee International Workshop on design and diagnostics of electronic circuits and systems

作者： Kothe, R. Vierhaus, H. T. Brandenburg Tech Univ Cottbus Inst Comp Sci POB 10 13 44 D-03013 Cottbus Germany

ISBN: (纸本)9781424411610

Fault tolerant design has recently gained new attention due to the increasing volatility of nano-electronic circuits from transient fault effects. Latches and flip-flops are the potential sources of errors. Novel designs of fault-tolerant flip-flops encompass multiple latches, which can also be used to accommodate the double-latched scan for dynamic test. the resulting scan-path elements are fault-tolerant for functional operation and static scan test.

关键词： Flip flop circuits

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