the paper deals withthe problems of logic function decomposition in Reed-Muller spectral domain. the Ashenhurst and the Curtis decompositions are considered. the decompositions are executed on Positive Polarization R...
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ISBN:
(纸本)9781424411610
the paper deals withthe problems of logic function decomposition in Reed-Muller spectral domain. the Ashenhurst and the Curtis decompositions are considered. the decompositions are executed on Positive Polarization Reed-Muller spectrum of decomposed functions. the elaborated methods of decomposition are guided to implementation of logic functions in LUT based FPGA. the results are very promising.
this paper(1) tries to find out whether commonly used spot defect fault model is still viable for Deep Sub-Micron (DSM) integrated circuits' test and yield model. It is believed that for DSM products spot defects ...
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ISBN:
(纸本)9781424411610
this paper(1) tries to find out whether commonly used spot defect fault model is still viable for Deep Sub-Micron (DSM) integrated circuits' test and yield model. It is believed that for DSM products spot defects may be no longer major source of yield loss. Results from number of computer experiments are presented and discussed.
the implementation and the fault simulation technique for the highly reliable digital design using two FPGAs under a processor control is presented. Two FPGAs are used for duplex system design, each including the comb...
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ISBN:
(纸本)9781424411610
the implementation and the fault simulation technique for the highly reliable digital design using two FPGAs under a processor control is presented. Two FPGAs are used for duplex system design, each including the combination of totally self-checking blocks based on parity predictors to obtain better dependability parameters. Combinatorial circuit benchmarks have been considered in all our experiments and computations. A Totally Self-Checking analysis of duplex system is supported by experimental results from our proposed FPGA fault simulator, where SEU-fault resistance is observed. Our proposed hardware fault simulator is compared also withthe software simulation. An area overhead of individual parts implemented in each FPGA is also discussed.
Reconfigurable computing has grown to become important in hardware design. In autumn 2005, we taught for the first time a new course in digital system design with its main focus on FPGA technology and design using VHD...
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ISBN:
(纸本)9781424411610
Reconfigurable computing has grown to become important in hardware design. In autumn 2005, we taught for the first time a new course in digital system design with its main focus on FPGA technology and design using VHDL. this paper reports about the various issues dealt with including what topics to cover, text book selection, lab exercises etc. A summary of the students feedback is also included.
In the work typical ESD failures of integrated circuits and ESD testing methods are presented. Authors describe dependencies between ESD models and different ESD failures. In order to allow more advanced ESD testing o...
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ISBN:
(纸本)9781424411610
In the work typical ESD failures of integrated circuits and ESD testing methods are presented. Authors describe dependencies between ESD models and different ESD failures. In order to allow more advanced ESD testing of integrated circuits, Transmission Line Pulsing is proposed and its correlation to HBM method described. Finally conclusions based on up-to-date research and test results obtained withthe help of the assembled TLP tester are provided.
this paper describes a new self-testing 1-bit full adder. this circuit consists of three polymorphic NAND/NOR gates, two XOR gates and two inverters. the adder is able to detect a reasonable number of stuck-at-faults ...
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ISBN:
(纸本)9781424411610
this paper describes a new self-testing 1-bit full adder. this circuit consists of three polymorphic NAND/NOR gates, two XOR gates and two inverters. the adder is able to detect a reasonable number of stuck-at-faults without the need of any additional logic and diagnostic signals. A fault is indicated by oscillations at the carry-out output. Properties of n-bit carry-propagate adder which is composed of the proposed 1-bit self-testing adders are investigated.
Withthe shrinking technology and increasing statistical defects, multiple design respins are required based on yield learning. Hence, a solution is required to efficiently diagnose the failure types of memory during ...
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ISBN:
(纸本)9781424411610
Withthe shrinking technology and increasing statistical defects, multiple design respins are required based on yield learning. Hence, a solution is required to efficiently diagnose the failure types of memory during production in the shortest time frame possible. this paper introduces a novel method of fault classification through image based prognosis of predefined fail signature dictionary. In contrary to the existing Bitmap Diagnosis methodologies, this method predicts the compressed failure map without generating and transferring complete Bitmap to the tester. the proposed methodology supports testing through a very low cost ATE. this architecture is partitioned to achieve sharing among various memories and at-speed testing.
Most of the early work on testing asynchronous combinational circuits ignored faults inside C elements, a common building block in these circuits. Using a standard cell based design, where C elements are built using m...
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ISBN:
(纸本)9781424411610
Most of the early work on testing asynchronous combinational circuits ignored faults inside C elements, a common building block in these circuits. Using a standard cell based design, where C elements are built using majority gates, we show that a number of faults are un-testable in some implementations, while others are undetected by previously proposed tests, which yield a fault coverage of only 70-80% even in the small circuits examined here. We present a novel test pattern generation algorithm based on the D algorithm and time-frame expansion that can automatically detect all testable stuck-at faults in these families of combinational asynchronous circuits. Finally we present a comparison of the test pattern lengths achieved by this method with previously published full-scan based methods.
this paper addresses an efficient concurrent fault detection scheme for the SBox hardware implementation of the AES algorithm. Concurrent fault detection is important not only to protect the encryption/decryption proc...
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ISBN:
(纸本)9781424411610
this paper addresses an efficient concurrent fault detection scheme for the SBox hardware implementation of the AES algorithm. Concurrent fault detection is important not only to protect the encryption/decryption process from random and production faults. It will also protect the system against side-channel attacks, in particular fault-based attacks, i.e. the injection of faults in order to retrieve the secret key. We will prove that our solution is very effective while keeping the area overhead very low.
Accurate analysis of CMOS gate power dissipation shows that amount of consumed energy depends on a reason of the gate switching. Number of activated inputs and type of applied signals have an influence on dynamic powe...
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ISBN:
(纸本)9781424411610
Accurate analysis of CMOS gate power dissipation shows that amount of consumed energy depends on a reason of the gate switching. Number of activated inputs and type of applied signals have an influence on dynamic power dissipation of the gate due to dynamic reconfiguration of internal gate parasitic capacitors. therefore, authors propose new modeling of dynamic power dissipation in static CMOS gates. Accurate modeling of dynamic power dissipation needs to take into consideration changes of all input signals. So, authors introduce new measure of digital circuit activity - gate driving way - for precise modeling of power dissipation. Based on conclusions flowing from the model analysis, authors propose method for two-level low-power circuitsdesign.
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