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10th ieee International Workshop on design and diagnostics of electronic circuits and systems

作者： Timar, Andras Rencz, Marta Budapest Univ Technol & Econ Dept Electron Devices 3 Goldmann Gyorgy Sq Budapest Hungary

ISBN: (纸本)9781424411610

In the past few decades, medical and biological researches gained more and more attention. the ever-growing need for such researches caused many medical applications to develop. Collecting data from a living human body is a complex task and needs circumspection. In this paper, specific issues of the most important part of such a data acquisition system is presented, the design of a low pass filter. the major issue to overcome in the design of a system that is aimed at being built into the human body is creating large value capacitances needed to the realization of filters for the specific application. After presenting the special requirements for low pass filters for medical applications the method of creating large capacitors is presented in details in the paper.

关键词： Low pass filters

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Architecture for highly reliable embedded flash memories

Architecture for highly reliable embedded flash memories

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10th ieee International Workshop on design and diagnostics of electronic circuits and systems

作者： Godard, Benoit Daga, Jean-Michel Torres, Lionel Sassatelli, Gilles ATMEL Embedded Non Volatile Memory Grp Libraries & Design Tools Dept F-13106 Rousset France Lab Informat Robot Montpellier France

ISBN: (纸本)9781424411610

Non-volatile embedded Flash (eFlash) memories are very popular in systems-on-a-Chip (SoC). these memories are based on the well-known floating gate concept. While densities and quality constraints are increasing, the reliability becomes a growing up issue. For eFlash memories, endurance and retention issues are at the root of reliability losses. To improve reliability, eFlash memories designs usually use techniques such as Error Correcting Codes (ECC), Redundancy and threshold Voltage (V-T) Analysis. In this paper, an implementation of these techniques is proposed through an architecture. thanks to eFlash specificity, the correction capacity is improved via a double correction scheme. Additionally, each time an operation is performed on a memory element, a smart reliability management tracks online errors and weak bits. When few issues in a word catch out the double error correction scheme, a Refresh and Repair with row redundancy process is engaged.

关键词： threshold voltage

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Analysis of noise margins due to device parameter variations in sub-100nm CMOS technology

Analysis of noise margins due to device parameter variations...

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10th ieee International Workshop on design and diagnostics of electronic circuits and systems

作者： Liang, Zhicheng Ikeda, Makoto Asada, Kunihiro Univ Tokyo Dept Elect Engn Bunkyo Ku 7-3-1 Hongo Tokyo 1138656 Japan

ISBN: (纸本)9781424411610

Increasing level of process variation in the sub-100nm silicon technology is becoming an important issue. In this paper we describe an approach to estimate the impact of process variations on the static CMOS and the dual-rail PLA down to 32nm process. this approach is built on accurate variation modeling, published data including the ITRS, Predictive Technology Models, and Monte-Carlo analysis. the analysis results show that a challenge due to insufficient noise margins is posed to the static CMOS at 32nm, and to the dual-rail PLA from 90nm. then a one-side virtual ground structure is also proposed to improve the noise margins of the dual-rail PLA. the improved dual-rail PLA is shown to work down to 32nm process with keeping an operational margin of 150mv.

关键词： CMOS integrated circuits

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Automatic generation of circuits for approximate string matching

Automatic generation of circuits for approximate string matc...

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10th ieee International Workshop on design and diagnostics of electronic circuits and systems

作者： Martinek, Tomas Fucik, Otto Beck, Patrik Lexa, Matej Brno Univ Technol Fac Informat Technol Bozetechova 2 Brno 61266 Czech Republic CESNET zspo Prague 160 Czech Republic Masaryk Univ Fac Informat Brno Czech Republic

ISBN: (纸本)9781424411610

Hardware accelerators for approximate string matching play an important role in an increasing number of modern bioinformatic applications. they are able to reduce the task complexity from quadratic to linear and show a speed up in orders of hundreds when compared with the respective software implementation. However, their wider use is limited by the lack of flexibility and modularity required by often variable tasks. In this respect, it is desirable to develop a procedure for automatic design and implementation of such accelerators' to reach high performance and efficiency typical for strongly optimized architectures, with as little human effort on the side of the designer as possible. this paper proposes the essential element of such a procedure, a method for the calculation of generic hardware architecture parameters. the proposed method is evaluated on a range of typical approximate string matching tasks. It demonstrates the differences in the designed architecture, when performance of individual tasks is maximized.

关键词： Timing circuits

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Cost-efficient synthesis for sequential circuits implemented using embedded memory blocks of FPGA's

Cost-efficient synthesis for sequential circuits implemented...

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10th ieee International Workshop on design and diagnostics of electronic circuits and systems

作者： Borowik, Grzegorz Falkowski, Bogdan Luba, Tadeusz Warsaw Univ Technol Inst Telecommun Nowowiejska 15-19 PL-00665 Warsaw Poland

ISBN: (纸本)9781424411610

Modern FPLD devices have a very complex structure. they combine PLA-like structures as well as FPGA's and even memory-based structures. However, the lack of an appropriate synthesis method does not allow the features of the modern FPLD's to be fully exploited. In this paper, an important problem of state assignment for an FSM as an extension of the previous research on ROM-based FSM implementation is presented. We pinpoint the sources of additional optimization of the functional decomposition and relate them to the state encoding conditions. the method is based on a reduction of a state assignment problem to a graph coloring problem. To this end, the so called multi-graph of incompatibility of memory T-words is applied. As a result, a new design technique for implementation of sequential circuits using embedded memory blocks of FPGA's has been developed. Preliminary experimental results are extremely encouraging.

关键词： Field programmable gate arrays (FPGA)

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Proposal of VLIW architecture for application specific processors with built-in-self-repair facility via variable accuracy arithmetic

Proposal of VLIW architecture for application specific proce...

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10th ieee International Workshop on design and diagnostics of electronic circuits and systems

作者： Pawlowski, Pawel Dabrowski, Adam Schoelzel, Mario Poznan Univ Tech Div Signal Proc & Elect Circuits Chair Control & Syst Engn Poznan Poland Brandenburg Tech Univ Cottbus Dept Comp Sci Cottbus Germany

ISBN: (纸本)9781424411610

A new proposal of a very long instruction word (VLIW) architecture for application specific processors with the built-in-self-repair (BISR) facility realized by means of the variable accuracy arithmetic has been described in this paper. the proposed idea, which is particularly interesting for the portable embedded systems, is based on a novel two accumulator model, which is used in order to obtain high accuracy of the result of a series of floating-point additions. the goal of the proposed approach consists in ensuring the functionality of the system even in case of permanent faults of particular building blocks, e.g., of one of the floating point adders. Instead of decreasing the performance of the system or providing redundant hardware, as it is typically done in other approaches' in our present concept merely the accuracy of the floating point accumulation is reduced. therefore, although the quality of service is reduced, the performance and the overall functionality of the system may remain unchanged. By this means we can also control the power consumption, saving the power with the cost of the somehow reduced signal processing accuracy.

关键词： Very long instruction word architecture

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Improving tolerance to power-supply and temperature variations in synchronous circuits

Improving tolerance to power-supply and temperature variatio...

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10th ieee International Workshop on design and diagnostics of electronic circuits and systems

作者： Semiao, J. Freijedo, J. Rodiriguez-Andina, J. J. Vargas, F. Santos, M. B. Teixeira, I. C. Teixeira, J. P. INESC ID Lisboa IST R Alves Redol 9 3 P-1000029 Lisbon Portugal Univ Algerve Sch Technol Faro Portugal Univ Vigo Dept Technol Elect Vigo Spain

ISBN: (纸本)9781424411610

As IC technology scales down, power supply voltage and temperature variations play an increasing role in signal integrity loss, which lead to performance degradation, reliability problems and functional errors. In this paper, we propose a new methodology to improve synchronous circuits' tolerance to power-supply voltage and temperature oscillations, without degrading its performance. the underlying principle of the proposed methodology is to introduce additional tolerance to the clock edge trigger in specific memory cells, by dynamically controlling the instant of occurrence of the clock edge trigger. the clock duty-cycle (CDC) is locally modulated, according to the signal propagation delay through the logic whose power supply voltage or temperature is being disturbed. the methodology is based on a clock stretching logic (CSL) block, used to dynamically modify the CDC, while maintaining at-speed clock rate. Moreover, when clock frequency reduction is inevitable, it improves circuit tolerance when the disturbances start to occur, allowing the clock generator to react and reduce its frequency. Experimental results based on SPICE simulations for two ITC99 benchmark circuits are used to demonstrate the usefulness of the proposed methodology.

关键词： signal integrity power-supply transient temperature variations tolerance signal propagation delay clock skew noise-adaptive clock duty-cycle

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Accelerating Yield Ramp through Real-Time Testing

Accelerating Yield Ramp through Real-Time Testing

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ieee symposium on On-Line Testing (IOLTS)

作者： Sanjiv Taneja Cadence Test Technology Group

With the increasing need for design specific yield optimization in nanometer technologies, it is becoming increasingly important to accelerate the identification of the root cause of systematic defects under very tight test cost constraints. this talk will give a high level overview of addressing these demanding challenges through a mix of cross-disciplinary EDA technologies spanning scan diagnostics, DFT, ATPG, BIST, DFM and real-time monitoring from ATE systems.

关键词： Life estimation Constraint optimization design optimization System testing Cost function electronic design automation and methodology Automatic test pattern generation Built-in self-test design for manufacture Real time systems

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Conference Reports

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ieee design & Test of Computers 2007年第3期24卷 294-295页

1. Latin-American Test Workshop--Victor Champac (National Institute for Astrophysics, Optics, and electronics)--the 8th ieee Latin-American Test Workshop was held 11-14 March 2007 in Cuzco, Peru. the technical program included regular papers, embedded tutorials, a panel session, and dedicated tutorials. the first day of the workshop was dedicated to the ieee Test Technology Educational Program (TTEP). A meeting was also held at LATW for those involved in the ALFA Project. 2. design and diagnostics of electronic circuits and systems--Patrick Girard (LIRMM), Andrzej Krasnewski (Warsaw University of Technology), Elena Gramatova (Slovak Academy of Sciences), and Adam Pawlak (Silesian University of Technology)--DDECS 2007 was held 11-13 April in Krakow, Poland. the technical program spanned three days of single-track sessions supported by three excellent keynote speeches. the program also included sponsor presentations, as well as the first annual presentation of the Jan Hlavicka Memorial award for outstanding paper by an East European author. In addition, DDECS was once again accompanied by the Challenges in Collaborative Engineering Workshop.

关键词： LATW DDECS Test design TTEP diagnostics Latin American electronic circuits And systems Jan Havlicka Memorial Award

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A 1.8 V 64 MHz Delta-Sigma Modulator for Wideband and Multi-Standard Applications

A 1.8 V 64 MHz Delta-Sigma Modulator for Wideband and Multi-...

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50th ieee International Midwest symposium on circuits and systems (MWSCAS'07), vol.3

作者： Y. Y. Du Kei-Tee Tiew Center for Integrated Circuits & Systems School of Electrical & Electronic Engineering Nanyang Technological University Singapore

this paper presents the design and implementation of a multi-standard wideband 6th-order delta-sigma modulator (DSM) operating at 1.8V supply. the three-stage 6th-order MASH (multi-stage noise shaping) DSM is proposed for operating at five different low oversampling ratios of 4, 6, 8, 12 and 16. the DSM is implemented using switched-capacitor circuits with a sampling frequency of 64MHz. the modulator uses 3-level quantizers in each stage and features optimized noise transfer function. the signal bandwidth achieved ranges from 2MHz to 8MHz with resolution of 13 bits to 8 bits respectively. the power consumption of the modulator is 27.5mW when operating at 64MHz. the size of the core IC is around 1mm{sup}2 in a 0.18μm single-poly, six-metal CMOS process.

关键词： Delta modulation Wideband Multi-stage noise shaping Switching circuits Switched capacitor circuits Sampling methods Frequency Integrated circuit noise Transfer functions Bandwidth

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