this paper presents a method for functional test generation, which aims self-test of RISC processors and process or cores. the method allows developing compact and quite effective software based tests if only the inst...
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ISBN:
(纸本)1424401844
this paper presents a method for functional test generation, which aims self-test of RISC processors and process or cores. the method allows developing compact and quite effective software based tests if only the instruction set architecture (ISA) or ISA together with some microarchitecture features are known. We have successfully applied this methodology to test a RISC processor core.
Technology forecasts predict that nanometer IC technologies will not yield large chip areas without non-functional transistors. Mechanism of redundancy and re-organization for self-repair at the transistor and gate le...
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ISBN:
(纸本)1424401844
Technology forecasts predict that nanometer IC technologies will not yield large chip areas without non-functional transistors. Mechanism of redundancy and re-organization for self-repair at the transistor and gate level are required, which can effectively handle realistic fault effects in CMOS logic circuits.
this paper presents FPGA implementations of traditional Almost Montgomery Inverse and Subtraction-free Almost Montgomery Inverse and compares their space and time properties. the subtraction-free algorithm with its ha...
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ISBN:
(纸本)1424401844
this paper presents FPGA implementations of traditional Almost Montgomery Inverse and Subtraction-free Almost Montgomery Inverse and compares their space and time properties. the subtraction-free algorithm with its hardware architecture overcomes the disadvantages of currently known methods (e.g. [2]). the ">" or "<" tests that require either extra clock cycles or extra chip area are completely eliminated.
We present two architectures of digit-serial normal basis multiplier over GF(2'''). the multipliers were derived from the multiplier of Agnew et al. Proposed multipliers are scalable by the digit width of ...
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ISBN:
(纸本)1424401844
We present two architectures of digit-serial normal basis multiplier over GF(2'''). the multipliers were derived from the multiplier of Agnew et al. Proposed multipliers are scalable by the digit width of general value in difference of the multiplier of Agnew et al. that may be scaled only by digit widththat divides the degree m. this helps designers to trade area for speed e.g. in pubhc-key cryptographic systems based on elliptic-curves, where m should be a prime number. Functionality of multipliers has been tested by simulation and implemented in Xilinx Virtex 4 FPGA.
this paper describes a design method for highly reliable digital circuits based on totally self checking blocks implemented in FPGAs. the dependability model and dependability calculations are proposed. the self check...
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ISBN:
(纸本)1424401844
this paper describes a design method for highly reliable digital circuits based on totally self checking blocks implemented in FPGAs. the dependability model and dependability calculations are proposed. the self checking blocks are based on a parity predictor. these blocks are linked together to form a compound design. Our adapted duplex system is used as a basic structure to increase availability parameters and protect system against Single Even Upsets (SEUs). this adapted duplex system is realized by two FPGAs, where each FPGA can be reconfigured when a fault is detected. Availability parameters have been calculated by dependability Markov models.
We present a survey on the academic and industrial structured ASIC practices, especially focusing on the test strategies currently in use. then, we compare two possible test generation flows, underlining the most crit...
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ISBN:
(纸本)1424401844
We present a survey on the academic and industrial structured ASIC practices, especially focusing on the test strategies currently in use. then, we compare two possible test generation flows, underlining the most critical aspects introduced by the adoption of the structured ASIC methodology.
this paper presents a scalable asynchronous dataflow processor. the main idea of the presented processor architecture is that the processing elements (PEs) are intelligent and can communicate directly with each other....
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ISBN:
(纸本)1424401844
this paper presents a scalable asynchronous dataflow processor. the main idea of the presented processor architecture is that the processing elements (PEs) are intelligent and can communicate directly with each other. A control element (CE) is used to solve possible conflicts between the data transferring of PEs and to control the execution of the program.
Extension of a BIST design algorithm is proposed in this paper. the method is based on a synthesis of a combinational block-the decoder, transforming pseudo-random code words into deterministic test patterns pre-compu...
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ISBN:
(纸本)1424401844
Extension of a BIST design algorithm is proposed in this paper. the method is based on a synthesis of a combinational block-the decoder, transforming pseudo-random code words into deterministic test patterns pre-computed by an ATPG tool. the column-matching algorithm is used to designthe decoder. Using this algorithm, maximum of decoder outputs is tried to be matched withthe decoder inputs, yielding the outputs be implemented as wires, thus without any logic. the newly proposed enhancement consists in a major generalization of the method. the ATPG possibility of generating more than one test vectors for one fault is exploited, yielding smaller area overhead. the complexity of the resulting BIST logic reduction is evaluated for some of the ISCAS benchmarks.
作者：
Kafka, LeosNovak, OndrejCTU
FEE Dept Comp Sci & Engn Karlovo Nam 13 Prague 12135 2 Czech Republic CAS
UTIA Dept Signal Proc Prague 18208 8 Czech Republic
Fault simulation allows evaluation of reliability properties of developed designs. the complexity of the designs is growing, which makes software-based simulation methods unusable. Hardware-based fault simulation can ...
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ISBN:
(纸本)1424401844
Fault simulation allows evaluation of reliability properties of developed designs. the complexity of the designs is growing, which makes software-based simulation methods unusable. Hardware-based fault simulation can bring desired speedup. Partial dynamic reconfiguration is a way of fault injection. Reconfiguration. time is often considered as a main weakness of this technique. this paper describes an FPGA-based fault simulator, where reconfiguration is performed by an embedded processor core, which eliminates this drawback. Error-detection-code based CED circuits are used in experiments;the results of the experiments are reported.
this paper presents a new, patent pending, random bit generator whose noise source exploits the leakage current in a reverse biased p-n junction. the circuit is described and a model is provided to estimate data-rate ...
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ISBN:
(纸本)1424401844
this paper presents a new, patent pending, random bit generator whose noise source exploits the leakage current in a reverse biased p-n junction. the circuit is described and a model is provided to estimate data-rate and expected quality of the generated bit sequence. Since the noise source is quasi-stateless, its deterministic evolution does not present complex patterns and therefore a lack of entropy and faults can be detected on-line.
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