Hardware accelerators for H.264/AVC using arithmetic coding require special approaches to achieve high throughputs. this paper proposes an efficient architecture for the context formatter that is a part of the H.264/A...
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ISBN:
(纸本)1424401844
Hardware accelerators for H.264/AVC using arithmetic coding require special approaches to achieve high throughputs. this paper proposes an efficient architecture for the context formatter that is a part of the H.264/AVC binary encoder. Five versions of the architecture are developed to match different throughputs. the implementation results show that the proposed versions of the context formatter match the performance of corresponding arithmetic coders.
In current hardware design flow, functional verification is widely acknowledged as the crucial step. this paper presents a new contribution to reduce the cost of this step by automating it. We address here, one of the...
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ISBN:
(纸本)1424401844
In current hardware design flow, functional verification is widely acknowledged as the crucial step. this paper presents a new contribution to reduce the cost of this step by automating it. We address here, one of the principal challenges of dynamic verification, by providing a new approach for automatic test generation. this approach combines mutation-based test techniques and genetic algorithms to produce stimuli for design under test. the feasibility of the proposed approach is assessed with a preliminary implementation, and some framework has been tested.
Field programmable gate arrays (FPGAs) provide a fast and flexible hardware for embedded control systems and signal processing. Despite this, tracing and monitoring of internal signals is awkward. FPGA vendors provide...
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ISBN:
(纸本)1424401844
Field programmable gate arrays (FPGAs) provide a fast and flexible hardware for embedded control systems and signal processing. Despite this, tracing and monitoring of internal signals is awkward. FPGA vendors provide their own tools to solve the debugging problems but they are not sufficient for real time monitoring. Instead, these signal tracing tools are good especially for tracing timing issues. this paper presents a method to monitor the internal signals of FPGA circuits by using an embedded microprocessor. the efficiency of this method is demonstrated with an FPGA-based active magnetic bearing control hardware.
Polymorphic gates exhibit one or more additional functions in addition to the "main" function of the gate. the additional functions can be activated under certain conditions by changing control parameters (s...
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ISBN:
(纸本)1424401844
Polymorphic gates exhibit one or more additional functions in addition to the "main" function of the gate. the additional functions can be activated under certain conditions by changing control parameters (such as temperature, Vdd, light etc.) of the circuit. this paper shows a non-trivial polymorphic combinational circuit (5 bit majority/Boolean symmetry) which was designed at the gate level and then simulated using polymorphic NAND/NOR gates controlled by Vdd and some conventional gates at the transistor level. PSpice simulations have shown correct behavior of this circuit.
this paper describes realization of a project that is concerned with a diagnostic system of a SOC. the diagnostic system used RESPIN architecture is based on the ieee 1500 standard and allows testing of cores by compr...
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ISBN:
(纸本)1424401844
this paper describes realization of a project that is concerned with a diagnostic system of a SOC. the diagnostic system used RESPIN architecture is based on the ieee 1500 standard and allows testing of cores by compressed test patterns. the patterns for certain core under test are decompressed in the scan chains of the other idle core during the test time. the compressed form of the test patterns is prepared by the algorithm COMPAS and stored in the memory of the SOC. the diagnostic system was implemented to the FPSLIC AT94K circuit that contain FPGA for cores, processor for control test procedure and the memory for storing the compressed test data in one system chip.
One-to-All Broadcast (OAB) and All-to-All Broadcast (AAB) [5] group communications are frequently used in many parallel algorithms and if their overhead is excessive, performance degrades rapidly with processor count....
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ISBN:
(纸本)1424401844
One-to-All Broadcast (OAB) and All-to-All Broadcast (AAB) [5] group communications are frequently used in many parallel algorithms and if their overhead is excessive, performance degrades rapidly with processor count. this paper deals withthe design of a new application specific Bayesian Optimization Algorithm (BOA) and Standard Genetic Algorithm (SGA) that both produce almost optimal communication schedules for an arbitrary multiprocessor topology. We demonstrated the optimization process on hypercube and AMP topology [1] using Wormhole (WH) switching.
Systolic array architectures for approximate string matching play a significant role as hardware accelerators in biological applications. However, their wider use is limited by the lack of flexibility required by ofte...
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ISBN:
(纸本)1424401844
Systolic array architectures for approximate string matching play a significant role as hardware accelerators in biological applications. However, their wider use is limited by the lack of flexibility required by often variable tasks. In this respect, it is desirable to develop a procedure for automatic design and implementation of such accelerators to reach high performance and efficiency with as little human effort on the side of the designer as possible. this paper proposes the essential element of such procedure, a method for the calculation of generic systolic array parameters with respect to maximal performance and efficient resource utilization.
In this paper, we present a methodology to evaluate the noise-induced logic error probability in a given CMOS digital design. the logic error probability is modeled in terms of the operating supply voltage, transistor...
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ISBN:
(纸本)1424401844
In this paper, we present a methodology to evaluate the noise-induced logic error probability in a given CMOS digital design. the logic error probability is modeled in terms of the operating supply voltage, transistor threshold voltage, input static probabilities, circuit configuration and noise level. At this stage of the work, the model is used to locate the weak-nodes against the noise within a design. the model is tested by comparing the results withthe transistor-level simulation at specific noise levels. the comparison shows that the model results fit well withthe simulation achieving speedup factor of more than 1000 times over the simulation tool. the simulation results have been obtained by using HSPICE, assuming 0.18 mu m CMOS technology.
systems on a Chip (SoCs) typically consist of several processor devices, embedded memory blocks, application-specific logic blocks and complex interconnects. While embedded memory blocks are mostly equipped with built...
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ISBN:
(纸本)1424401844
systems on a Chip (SoCs) typically consist of several processor devices, embedded memory blocks, application-specific logic blocks and complex interconnects. While embedded memory blocks are mostly equipped with built-in self test (BIST) capabilities, test methods for processors, logic blocks and interconnects are still topics of intensive research. Beyond production testing, SoCs in safety-critical applications also need built-in self test capabilities, which work independently from external control hardware. A HW/SW -based self test scheme can facilitate self test in the field of application making efficient use of structures for production test and can even supplement production test, e. g. for internal interconnects. the paper describes the architecture, cost and limitations.
this paper introduces a Multiple Valued Counter, based on recharged semi floating gate structures. the counter starts at a sampled voltage, and counts from there, using an input clock signal as an input. Depending on ...
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ISBN:
(纸本)1424401844
this paper introduces a Multiple Valued Counter, based on recharged semi floating gate structures. the counter starts at a sampled voltage, and counts from there, using an input clock signal as an input. Depending on the sampled value and the phase of the input clock signal-the counter can count both up and down. the counting steps can be varied adjusting the input clock amplitude, which in combination with different output resetting values allows a set of different counting radixes. Recharged semi floating structures may suffer from an offset at the output due to mismatch in the inverter structures. this counter minimizes this problem with a build in offset cancellation, which is an advantage for non capacitive readouts.
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