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检索条件"任意字段=13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

共 683 条记录，以下是61-70 订阅

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Duality and resonance in RLC–circuits. Exact formulas for phase, amplitude resonance and bandwidth

Duality and resonance in RLC–circuits. Exact formulas for p...

引用

ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Daniel Blokhin Institute of Engineering and Information Technologies Kyiv National University of Technologies and Design Kyiv Ukraine

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

the paper is devoted to the study of two-terminal electric circuits consisting of three elements - a resistor, a capacitor, and an inductor. there are eight different possible combinations of such circuits. We apply a standard and nonstandard duality (frequency duality). In this way, all possible circuits are divided into three groups: (2+ 2 +4). the first pair of circuits is extensively covered in most electrical engineering textbooks. the second pair is not interesting from the frequency point of view. We investigate in detail a third group of four circuits, which, by suitable substitution of variables, bring the finding of their frequency characteristics to the study of a single function. For them we find exact formulas for the frequency of phase resonance and amplitude resonance. the values of the minimum (maximum) amplitude at the corresponding resonance frequencies are found. Exact and approximate formulas for the cut-off frequency and bandwidth of the passband-stopband transition are derived.

关键词： Resistors circuits Resonant frequency RLC circuits Bandwidth Linear circuits Resonance Inductors Standards electronic circuits

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Domain-Specific design Abstraction with Emphasis on Neural Networks

Domain-Specific Design Abstraction with Emphasis on Neural N...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Maryam Rajabalipanah Zahra Hojati Zahra Jahanpeima Zainalabedin Navabi School of Electrical and Computer Engineering College of Engineering University of Tehran Tehran Iran

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

the increasing complexity in digital system design has introduced significant challenges, particularly in maintaining productivity relative to the rapid advancement of technology. this paper addresses the issue by presenting a new level of abstraction, termed Data Transaction Level (DTL), which operates at a higher level than the traditional Register Transfer Level (RTL). the proposed DTL design methodology draws inspiration from RTL but is tailored for the growing complexity of modern systems, particularly in neural network implementations. As neural networks are becoming essential in various applications, this paper applies the DTL methodology to hardware implementations of these networks. A SystemC-based hardware description language is introduced to facilitate the design process. the results section evaluates the effectiveness of the proposed methodology, highlighting increased productivity using the new abstraction and description language.

关键词： Productivity Industries Digital systems design methodology Neural networks Register transfer level Hardware Complexity theory Hardware design languages electronic circuits

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Optimization of Imprecise Multiplier circuits by using Binary Decision Diagram 9

Optimization of Imprecise Multiplier Circuits by using Binar...

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9th ieee International symposium on Smart electronic systems, iSES 2023

作者： Choudhary, Pooja Bhargava, Lava Vinod, G.U. Suhag, Ashok Kumar Fujita, Mashahiro Singh, Virendra Swami Keshvanand Institute of Technology Management and Gramothan Dept. of Electronics and Communication Engineering Jaipur India Malaviya National Institute of Technology Jaipur India Malaviya National Institute of Technology Dept. of Electronics and Communication Engineering Jaipur India Qualcomm Bangalore India Bml Munjal University Dept. of Electronics and Communication Engineering Haryana India Vlsi Design and Education Center University of Tokyo Japan Indian Institute of Technology Dept. of Electrical Engineering Dept. of Computer Science Engineering Bombay India

ISBN: (纸本)9798350383249

Imprecise multipliers are employed to enhance the efficiency and reduce the power consumption of arithmetic circuits while tolerating acceptable levels of inaccuracy in the outcomes. the multiplier circuit has a broader range of applications within embedded systems, particularly in the fields of digital signal processing, IoT and multimedia, etc. We proposed a systematic formal approach utilizing the Look-Up Table (LUT) employing the Burch method to evaluate the imprecise multiplier based on the Binary Decision Diagram (BDD) considering Worst Case Error constraint. Implemented 13 bit multiplier using normal and proposed imprecise multiplier shows 98% reduction in number of nodes. the proposed 25 bit imprecise multiplier based on Burch HL shows an 89% decrement in a number of nodes w.r.t. Burch LH method. BDD generation for imprecise multiplier is 75% faster than normal. © 2023 ieee.

关键词： Timing circuits

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A Parameterizable Chisel Generator of Numerically Controlled Oscillators for Direct Digital Synthesis 24

A Parameterizable Chisel Generator of Numerically Controlled...

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24th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Damnjanovic, Vukan D. Petrovic, Marija L. Milovanovic, Vladimir M. Univ Kragujevac Fac Engn Sestre Janjic 6 Kragujevac Serbia NOVELIC Veljka Dugosevica 54 Belgrade Serbia

ISBN: (纸本)9781665435956

Numerically controlled oscillators (NCOs) as part of direct digital synthesizers (DDS) are important components in many digital communication subsystems, such as various digital modulation and demodulation schemes, up and down converters, radar, sonar and laser appliances, etc. the vast number of their beneficial characteristics is what makes NCOs so widely used. Taking this into account, a parameterizable generator of numerically controlled oscillators is implemented using Chisel hardware design language. the proposed generator provides a broad range of parameter configurations, such as input and output data types and widths, the number of different output samples, optional use of spur-reducing techniques or different input interfaces, just to name a few. Numerous generated instances have been tested in software simulations and mapped and tested onto a commercial FPGA platform. Obtained results proved that a generator of this kind can legitimately be compared with custom designed NCO modules, both in terms of performance and resource utilization.

关键词： Numerically controlled oscillator direct digital synthesizer Chisel hardware design language design generator

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Using Model Checker to Analyze and Test Digital circuits with Regard to Delay Faults 24

Using Model Checker to Analyze and Test Digital Circuits wit...

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24th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Strnadel, Josef Brno Univ Technol Fac Informat Technol Brno Czech Republic

ISBN: (纸本)9781665435956

Narrow timing margins in modern digital circuits result in delay defects that are difficult to detect. the probability that such a defect occurs increases with factors such as shrinking feature sizes, increasing process variations, operating frequencies, and aging/stress of the circuits. Traditionally, timing is considered in connection with the logic design, physical design and layout, and delay testing phases of the circuit development process and builds on principles of delay characterization, fault models and timing analysis. this paper presents a model checking approach aiming to facilitate the solutions of problems with regard to analyzing consequences and testing of delay faults. Our approach expects that a circuit is modeled as a network of stochastic hybrid timed automata capable to describe the circuit both in the logical and temporal domains, including facts such as uncertainty and variations. In our approach, we gather attributes and formalize expected properties of a circuit and transform the circuit into our model. then, we use a statistical model checker to check the properties and to produce a counter-example for each property being violated. Further, we transform the counter-examples into test cases and finally, into a delay test able to check whether the timing requirements are met.

关键词： digital circuit timing delay fault timed automaton model checking counter-example test case test

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Synthesis of approximate circuits for LUT-based FPGAs 24

Synthesis of approximate circuits for LUT-based FPGAs

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24th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Vasicek, Zdenek Brno Univ Technol Fac Informat Technol IT4Innovat Ctr Excellence Brno Czech Republic

ISBN: (纸本)9781665435956

Approximate computing is an emerging paradigm that trades the accuracy of computation to achieve gain in terms of design area, critical path delay and/or power consumption. there is a rich body of literature showing that the approximate hardware components serving as basic building blocks for energy-efficient implementation of complex systems offer a remarkable gain in efficiency and/or performance in exchange for small losses in output quality. However, recent studies revealed that the approximate components optimized mainly for ASICs offer asymmetric gain when used in FPGAs. In this work, we present an iterative design method for automated synthesis of elementary approximate components natively optimized for usage in LUT-based FPGAs. the method takes into account the number of LUTs and LUT-level propagation delay instead of the number of gates and logic levels typically considered in other works. Using this method, we synthesized various approximate adders (up to 64-bit) and multipliers (8-bit and 16-bit). Compared to the current state-of-the-art, our designs achieve better trade-off when considered the worst case absolute error, number of LUTs and propagation delay. the discovered approximate adders and multipliers are available online in the form of Verilog netlists consisting of 4, 5 and 6-input LUTs.

关键词： Field programmable gate arrays (FPGA)

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Behavioral Model of Dot-Product Engine Implemented with 1T1R Memristor Crossbar Including Assessment 24

Behavioral Model of Dot-Product Engine Implemented with 1T1R...

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24th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Wen, Jianan Ulbricht, Markus Perez, Eduardo Fan, Xin Krstic, Milos IHP Leibniz Inst Innovat Mikroelekt Frankfurt Oder Germany Rhein Westfal TH Aachen Aachen Germany Univ Potsdam Potsdam Germany

ISBN: (纸本)9781665435956

Memristor is an emerging electrical device that enables non-volatile storage and in-memory computing. the memristive crossbar with high memory density and low energy consumption has drawn much attention for the implementation of dot-product engines, which can be deployed in power-hungry applications with intensive multiply-accumulate operations. However, simulating the crossbar containing a group of memristors based on the device-level modeling is time consuming. In this paper, we propose a model to simulate the memristive crossbar with high flexibility and automation at the behavioral level to perform the vector-matrix multiplication. this system-level model captures the non-linearity of memristors aiming for fast and accurate simulation. With the significantly reduced simulation time, this model enables simulating the systems containing memristive crossbar with large scale like neural networks in a more practical way. Moreover, this model can be exploited to analyze the effects of variations, which provides a condition and contributes to revealing potential computational errors. A multilayer perceptron detecting breast cancer is simulated based on this model to assess the classification accuracy with the presence of variabilities.

关键词： Memristive crossbar dot-product engine behavioral model neural network variability modeling

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A Survey on Automatic Assertion Miners

A Survey on Automatic Assertion Miners

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Mohammad Reza Heidari Iman Giorgio Di Natale Katell Morin-Allory CNRS Institut National Polytechnique Grenoble Alpes TIMA Univ. Grenoble Alpes Grenoble France

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

In the area of functional verification, AssertionBased Verification (ABV) has gained significant attention for the advantages it provides in verifying hardware designs. this approach relies on assertions generated by automatic assertion miners. these miners employ various techniques and methods to automatically mine assertions. this paper focuses on studying the most recent, advanced, and widely used assertion miners in the field and provides an analytical comparison between them. this study aims to highlight the strengths and shortcomings of current automatic assertion miners to assist researchers and verification engineers in understanding the functionality, strengths, and limitations of each miner. By addressing these limitations, more advanced automatic assertion miners can be developed in the future.

关键词： Surveys Focusing Hardware electronic circuits

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Accuracy Enhancement of Resistor-String Digital-to-Analog Converters through Averaging Dynamic Element Matching

Accuracy Enhancement of Resistor-String Digital-to-Analog Co...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Francesco Gagliardi Michele Dei Department of Information Engineering University of Pisa Pisa Italy

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

In integrated Digital-to-Analog Converters (DACs), random mismatch errors among nominally equal unit elements significantly limit the achievable accuracy. this work explores the effectiveness of tailored Dynamic Element Matching (DEM) techniques in mitigating mismatch-induced non-linearity errors in resistor-string DAC architectures. through statistical behavioural simulations, we identify effective DEM strategies that substantially reduce Integral Non-Linearity (INL). the proposed technique enables virtually zero INL errors at specific points of the transfer characteristic, which can be strategically chosen during circuit operation. Insofar, optimized design approaches for resistor-string DACs are proposed, fostering future integratedcircuit implementations with superior yield concerning accuracy and linearity specifications.

关键词： Resistors Accuracy Digital-analog conversion Linearity Integrated circuit modeling electronic circuits

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Enhanced Reliability of Fully Differential Difference Amplifier through On-chip Digital Calibration 24

Enhanced Reliability of Fully Differential Difference Amplif...

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24th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Maljar, David Sovcik, Michal Arbet, Daniel Stopjakova, Viera Slovak Univ Technol Bratislava Inst Elect & Photon Fac Elect Engn & Informat Technol Bratislava Slovakia

ISBN: (纸本)9781665435956

this paper presents a novel on-chip digital method of calibration for a fully differential difference amplifier (FDDA), which is aimed at improved performance and reliability through enhanced robustness against variations of process parameters, voltage, temperature, and ageing drift. the proposed method was designed and verified within 130 nm CMOS technology design kit in Cadence environment. Calibration hardware is built-in with the calibrated FDDA, and the whole integrated system is able to operate with only 0.4 V power supply. the effectiveness of the proposed calibration method was examined mainly by evaluation of the FDDA input offset voltage using Monte Carlo, process corners and ageing analyses performed for the temperature range from -20 degrees C to 85 degrees C. the work established metrics for comparison of different calibration methods (i.e. digital calibration, chopper stabilization, analog calibration and autozero), which significantly differ in fundamentals of their operation. the proposed digital calibration outperforms its alternatives, while the precision of calibration, area and power consumption overhead are considered. the less advanced topology of digital calibration was previously implemented for variable-gain amplifier with considerable success (residual offset of the calibrated amplifier reaches fair levels of 13 mu V to 167 mu V). the concept proposed in this work utilizes advanced high precision calibration algorithm.

关键词： digital calibration PVTA variations high reliability high precision compensation input offset voltage ultra-low voltage design

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