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检索条件"任意字段=13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

共 683 条记录，以下是71-80 订阅

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FPGA Architectures of the Quantization and the Dequantization for Video Encoders 17

FPGA Architectures of the Quantization and the Dequantizatio...

引用

ieee 17th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Pastuszak, Grzegorz Warsaw Univ Technol Inst Radioelect PL-00665 Warsaw Poland

ISBN: (纸本)9781479945580

In hardware video encoders, the quantization and dequantization modules can consume a significant amount of hardware resources. this paper presents optimization methods for FPGA architectures of the modules. the methods allow a better utilization of resources available in DSP units and the reduction of general-purpose logic elements. Different versions of architectures are developed for FPGA Altera Arria II devices. Implementation results show that the multiple reduction of general-purpose logic is achieved. Moreover, the utilization of registers embedded in DSP allows the doubled clock frequency.

关键词： FPGA Architecture design Video Coding H.264/AVC H.265/HEVC Quantization

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Intelligent IGBT driver concept or three-phase electric drive diagnostics

Intelligent IGBT driver concept or three-phase electric driv...

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13th ieee International symposium on design and diagnostics of electronic circuits and systems, DDECS 2010

作者： Klima, B. Knobloch, J. Pochyla, M. Department of Power Electrical and Electronic Engineering Faculty of Electrical Engineering and Communication Brno University of Technology Brno Czech Republic

ISBN: (纸本)9781424466139

this document focuses on he problem of diagnostics of an electrical drive equipped with a voltage source inverter (VSI) the attention is concentrated on a hardware design or a power system diagnostics A new concept of a power transistor driver is proposed. this concept of he driver integrates functions for monitoring of a large number of electrical drive parameters which are transferred to the superior control system for an actual operation state evaluation or an eventual failure state detection. the proposed solution introduces the possibility of an internal electrical quantities feedback realization (phase currents and DC link voltage) directly in the drivers of power transistors without using standard current and voltage sensors the feed-backs can be extended with output voltages measurement of the inverter which can be further used in online identification of motor parameters for a model of the electrical drive. this model can be used for a control technique adaptation (with respect to maximal efficiency, maximal dynamic performance or also or sensor-less peed control or position control). © 2010 ieee.

关键词： Insulated gate bipolar transistors (IGBT)

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A Novel Impedance Calculation Method and its Time Efficiency Evaluation 17

A Novel Impedance Calculation Method and its Time Efficiency...

引用

ieee 17th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Brenkus, Juraj Stopjakova, Viera Arbet, Daniel Gyepes, Gabor Majer, Libor Slovak Univ Technol Bratislava Inst Elect & Photon Dept IC Design & Test Bratislava Slovakia

ISBN: (纸本)9781479945580

A novel resistance calculation method based on eigen calculus of the circuit's nodal admittance matrix is described and evaluated in this paper. More specifically, the calculation time efficiency of the method is examined and comparison to the traditional LU factorization based method is made. this evaluation is based on real and complex matrices that are both symmetrical and non-symmetrical as well. circuits sizes taken into account range from 25 to 3600 nodes. the obtained results demonstrate the time efficiency of this method, especially, for non-symmetrical matrices. the proposed method could be used to speed-up the fault simulations and improve test development of analog circuits.

关键词： impedance calculation analog circuit fault analysis

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design of a scalable asynchronous dataflow processor

Design of a scalable asynchronous dataflow processor

引用

9th ieee Workshop on design and diagnostics of electronic circuits and systems

作者： Lampinen, Harri Perala, Pauli Vainio, Olli Tampere Univ Technol Inst Digital & Comp Syst POB 553 FIN-33101 Tampere Finland

ISBN: (纸本)1424401844

this paper presents a scalable asynchronous dataflow processor. the main idea of the presented processor architecture is that the processing elements (PEs) are intelligent and can communicate directly with each other. A control element (CE) is used to solve possible conflicts between the data transferring of PEs and to control the execution of the program.

关键词： Program processors

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Implementation of a Real Time Unit for Satellite Applications 19

Implementation of a Real Time Unit for Satellite Application...

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ieee 19th International symposium on design and diagnostics of electronic circuits & systems (DDECS)

作者： Simevski, Aleksandar Schleisiek, Klaus Petrovic, Vladimir Beller, Norbert Skoncej, Patryk Schoof, Gunter Krstic, Milos IHP Technol Pk 25 D-15236 Frankfurt Oder Germany SpaceTech Seelbachstr 13 D-88090 Immenstaad Germany

ISBN: (纸本)9781509024674

the significance of low cost small satellites used for scientific research and practical applications continuously grows. Current satellite OBC (On-Board Computer) microcontrollers have integrated various digital peripherals and interfaces. However, a common Real Time Unit (RTU) requires interfacing to simple analogue sensors and actuators. Here we present a novel RTU microcontroller which includes a 13-bit Analog-to-Digital Converter (ADC) and two 12-bit Digital-to-Analog Converters (DAC). Furthermore, it includes a 32KB internal SRAM memory and a 32KB internal flash memory. this enables an easy construction of a software-controlled embedded system which is easily interfaced to existing hardware sensors and actuators. the chip is produced in IHP 250nm technology using radiation hardening by design. the operating frequency is 80 MHz. A 3-bit clock divider, as well as clock-and power-gating are used for reducing power consumption which is measured to be 0,8W in operation.

关键词： Microcontrollers

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Decomposition of logic functions in Reed-Muller spectral domain

Decomposition of logic functions in Reed-Muller spectral dom...

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10th ieee International Workshop on design and diagnostics of electronic circuits and systems

作者： Hrynkiewicz, Edward Kolodzinski, Stefan Silesian Tech Univ Inst Elect Gliwice Poland

ISBN: (纸本)9781424411610

the paper deals with the problems of logic function decomposition in Reed-Muller spectral domain. the Ashenhurst and the Curtis decompositions are considered. the decompositions are executed on Positive Polarization Reed-Muller spectrum of decomposed functions. the elaborated methods of decomposition are guided to implementation of logic functions in LUT based FPGA. the results are very promising.

关键词： Computer circuits

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A hardware accelerated framework for the generation of design validation programs for SMT processors

A hardware accelerated framework for the generation of desig...

引用

13th ieee International symposium on design and diagnostics of electronic circuits and systems, DDECS 2010

作者： Ravotto, D. Sánchez, E. Sonza Reorda, M. Politecnico di Torino Dipartimento di Automatica e Informatica Torino Italy

ISBN: (纸本)9781424466139

In this paper, we propose an innovative emulation-based framework for the generation of test programs oriented to SMT microprocessor validation. the two major characteristics of the proposed framework are an effective method to gather information about the processor internal status via its emulation, and an efficient algorithm which exploits these pieces of information for a generation process which is particularly suited for SMT processors. Performance counters (PCs) as well as ad hoc registers are used to achieve the former result, while a feedback-based generation process is devised to achieve the latter. Experimental results gathered on a real complex design (the OpenSPARC™ T1 core) show that the proposed framework can achieve high quality results with acceptable CPU time and human effort requirements. © 2010 ieee.

关键词： Software testing

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A design of ring oscillator based PUF on FPGA 18

A design of ring oscillator based PUF on FPGA

引用

ieee 18th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Kodytek, Filip Lorenez, Robert Czech Tech Univ Dept Comp Syst Thakurova 9 Prague Czech Republic

ISBN: (纸本)9781479967803

this paper deals with design of Physical Unclonable Functions (PUFs) based on FPGA. the goal was to propose a cheap, efficient and secure device identification or even a cryptographic key generation based on PUFs. therefore, a proposal of a ring oscillator (RO) based PUF producing more output bits from one RO pair is presented. 24 Digilent Basys 2 FPGA boards were tested and statistically evaluated indicating suitability of the proposed design for device identification.

关键词： PUF FPGA ring oscillator

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Multiple-vector column-matching BIST design method

Multiple-vector column-matching BIST design method

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9th ieee Workshop on design and diagnostics of electronic circuits and systems

作者： Fiser, Petr Kubatova, Hana Czech Tech Univ Dept Comp Sci & Engn Karlovo Nam 13 Prague 12135 2 Czech Republic

ISBN: (纸本)1424401844

Extension of a BIST design algorithm is proposed in this paper. the method is based on a synthesis of a combinational block-the decoder, transforming pseudo-random code words into deterministic test patterns pre-computed by an ATPG tool. the column-matching algorithm is used to design the decoder. Using this algorithm, maximum of decoder outputs is tried to be matched with the decoder inputs, yielding the outputs be implemented as wires, thus without any logic. the newly proposed enhancement consists in a major generalization of the method. the ATPG possibility of generating more than one test vectors for one fault is exploited, yielding smaller area overhead. the complexity of the resulting BIST logic reduction is evaluated for some of the ISCAS benchmarks.

关键词： Built-in self test

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Test and Diagnosis of Power Switches 17

Test and Diagnosis of Power Switches

引用

ieee 17th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Valka, M. Bosio, A. Dilillo, L. Todri, A. Virazel, A. Girard, P. Debaud, P. Guilhot, S. Univ Montpellier 2 CNRS LIRMM Montpellier France ST Microelect Grenoble France

ISBN: (纸本)9781479945580

Power-gating techniques have been adopted so far to reduce the static power consumption of an Integrated Circuit (IC). Power gating is usually implemented by means of several power switches. Manufacturing defects affecting power switches can lead to increase the actual static power consumption and, in the worst case they can completely isolate a functional block of the IC. In this paper we present a novel design for Test & Diagnosis to increase the test quality and diagnosis accuracy of power switches. the proposed approach has been validated through SPICE simulations on ITC'99 benchmark circuits.

关键词： Power Switch Power Management design for Test & Diagnosis

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