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检索条件"任意字段=13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

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Structured design and Evaluation of a Resistor-Based PUF Robust Against PVT-Variations

Structured Design and Evaluation of a Resistor-Based PUF Rob...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Carl Riehm Christoph Frisch Florin Burcea Matthias Hiller Michael Pehl Ralf Brederlow TUM School of Computation Information and Technology Technical University of Munich Munich Germany Fraunhofer AISEC Garching Germany

this paper proposes a new fully CMOS-compatible PUF primitive robust against process variations, supply voltage variations and temperature drift (PVT) based on resistive structures that implements advanced compensation mechanisms already on circuit level. Based on analog simulation data, the PUF is evaluated regarding its unpredictability and its reliability. the results indicate a high quality. Further, a structured approach for designing a suitable error correction is presented to illustrate the whole PUF system.

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ABACUS: ASIP-Based Avro Schema-Customizable Parser Acceleration on FPGAs

ABACUS: ASIP-Based Avro Schema-Customizable Parser Accelerat...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Tobias Hahn Daniel Schüll Stefan Wildermann Jürgen Teich Hardware/Software Co-Design Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU) Germany

Big Data applications frequently process data streams encoded in semi-structured data formats such as JSON, Protobuf, or Avro. Parsing these data formats into a representation to then be processed by a CPU frequently takes up a major share of the processing time. As a remedy, JSON and Avro FPGA accelerators have been introduced that can parse the data directly in the data path, offloading this workload from the CPU without requiring any additional data movement. However, these accelerators are schema-specific circuits that require time-consuming resynthesis processes for schema adaptations. this is particularly critical in Big Data applications, where multiple schemas may be in use simultaneously. As a remedy, we present an application-specific instruction set processor (ASIP) architecture for parsing Avro data on FPGAs. An instruction program controls the ASIP to parse a specific schema. Any schema change therefore only requires the loading of a new instruction sequence into an instruction memory. It is also shown that this approach is more resource-efficient than related work, as functional units only need to be instantiated once for each Avro data type. Our experimental evaluation shows that we can achieve a throughput of 707–818 MB/s per kLUT which is about 7 to 14 times higher than the throughput per LUT achieved in related work.

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S4V: A Benchmark Suite of Transient Execution Attacks for RISC-V Processors

S4V: A Benchmark Suite of Transient Execution Attacks for RI...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Elia Lazzeri Matteo Colella Gianluca Furano Luca Cassano Politecnico di Milano Milano Italy European Space Agency Noordwijk The Netherlands

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

Transient Execution Attacks (TEAs) exploit architectural optimizations in modern processors, such as out-of-order and speculative execution, to illicitly access sensitive data belonging to other processes or the operating system. While the RISC-V ISA has gained significant traction, its susceptibility to TEAs remains relatively unexplored. A major obstacle to in-depth security evaluation of RISC-V processors is the lack of readily accessible and comprehensive TEA implementations for these architectures. this paper introduces Security for RISC-V (S4V), a security benchmark suite comprising implementations of several recent TEAs specifically tailored for RISC-V processors. Beyond providing a template for each TEA implementation, we developed an instance of S4V for the Berkeley Out-of-Order Machine (BOOM) processor to demonstrate the feasibility of executing these attacks on a widely adopted and renowned RISCV core. S4V aims to facilitate security research in evaluating countermeasures and enabling a more thorough understanding of TEA vulnerabilities within the RISC-V ecosystem.

关键词： Out of order Program processors Operating systems Microprocessors Hardware security Benchmark testing Transient analysis electronic countermeasures Optimization electronic circuits

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Implementation of Dynamic SISD-SIMD Integer Dividers

Implementation of Dynamic SISD-SIMD Integer Dividers

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Gianluca Radi Ares Tahiraga Robert Kunzelmann Ties Jan Henderikus Kluter Wolfgang Ecker Processor Architecture Laboratory EPFL Lausanne Switzerland Infineon Technologies AG Neubiberg Germany

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

Digital division is a pivotal operation in a number of domains, such as scientific computation, cryptography, digital signal processing, and machine learning, and has been broadly researched in the past decades. However, the increasing demand for efficient digital systems has emphasized the design of digital dividers with more stringent area and power costs without excessively compromising their performance. One option to achieve this is to implement Single Instruction Multiple Data (SIMD) dividers capable of exploiting the abundance of data-level parallelism, which is naturally present in common tasks such as stream processing, matrix normalization, and vector scaling. In this paper, we propose the designs of four configurable integer dividers capable of sustaining both Single Instruction Single Data (SISD) and SIMD computations, targeting different levels of performance and efficiency. Compared to one of the state-of-the-art integer dividers, our most efficient SIMD divider shows a 54% smaller area and 30% lower power consumption. Furthermore, we propose a novel technique which can reduce n-bit divisions to smaller (n−m)-bit ones, yielding a peek speedup of 15% when implemented in one of our proposed dividers.

关键词： Costs Power demand Single instruction multiple data Digital systems Machine learning Digital signal processing Frequency conversion Vectors Cryptography electronic circuits

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Evaluating the Hardware Performance Counters of an Xtensa Virtual Prototype

Evaluating the Hardware Performance Counters of an Xtensa Vi...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Adebayo Omotosho Sirine IIahi Ernesto Cristopher Villegas Castillo Christian Hammer Christian Sauer University of Central Lancashire Preston United Kingdom University of Passau Passau Germany Cadence Design Systems Munich Germany

Embedded systems’ hardware and software stacks are becoming more complex requiring more development time, time to market, and cost, which contributes to delayed delivery of these silicon devices. A virtual prototype (VP) provides an embedded systems architecture simulator for application development and testing purposes. In this paper, we developed and present the first virtual prototype of the Xtensa LX7 microprocessor that evaluates the performance of its emulated hardware performance counters (HPCs) with those collected from an actual Xtensa LX7 hardware. Seven machine learning models were developed and trained to find the relationships between the two different datasets for the sample application of classifiying return-oriented programming (ROP) attacks. Our experiments show that the obtained micro-architectural characteristics on the VP are on average about 70% similar and thus permit early simulation capabilities for developers and testers.

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Standalone Area Optimized ASIC Tag Powered and Programmable by Light for Identification of Novel Drug Candidates

Standalone Area Optimized ASIC Tag Powered and Programmable ...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Dominic Korner Andreas Kramer Klaus Hofmann Felix Hausch Integrated Electronic Systems Lab Technische Universität Darmstadt Germany Darmstadt Institute of Organic Chemistry and Biochemistry Technische Universität Darmstadt Germany Darmstadt

We present a compact optical programmable ASIC-based tag for the identification of novel drug candidates, requiring no external components. Our tag aims for a time and cost-efficient solution to keep track of compounds during the split and pool synthesis. the ASIC is self-powered by integrated solar cells and optimized for intensive light in the range of 10Mlx. this intensive illumination can cause unwanted leakage currents in p-n junctions. therefore, extensive care was taken to provide shielding for sensitive parts of the circuit and measurements prove the effectiveness. the ASIC is manufactured in a 0.6µm process including special devices like EEPROM and photodiodes. Our tag contains an oscillator, optical receiver, reference voltage, and a digital controller. A custom optical communication protocol provides an energy-efficient data link to the smart tag with continuous power transfer.

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Characterization of Interconnect Fault Effects in SRAM-based FPGAs

Characterization of Interconnect Fault Effects in SRAM-based...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Christian Fibich Martin Horauer Roman Obermaisser Dept. of Electronic Engineering UAS Technikum Wien Vienna Austria Chair for Embedded Systems University of Siegen Siegen Germany

the configurable interconnect of SRAM-based FPGAs makes up a significant portion of their configuration, and thus exposes a large attack surface to single-event upsets. A better understanding of the behavior of FPGA interconnects under the presence of these faults may allow fault injection campaigns and reliability estimation techniques to treat some interconnect faults as more serious than others. this work proposes an approach to (1) analyze the interconnect configuration of a given FPGA technology to deduce the logical effects caused by single-bit flips and (2) to characterize the effects of such faults on routes implemented on a given FPGA technology. these approaches are illustrated in case studies on two FPGA technologies: Xilinx 7 Series and Lattice iCE40. Characterization of interconnect faults on these devices revealed that certain subcategories of interconnect fault types are far more critical than others, allowing more focused fault injection campaigns. Applying this knowledge to three benchmark designs implemented on a Xilinx 7 Series device shows that fault injection effort can be significantly reduced by skipping bits that are unlikely to critically impact the design.

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MODEE-LID: Multiobjective design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers

MODEE-LID: Multiobjective Design of Energy-Efficient Hardwar...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Martin Hurta Vojtech Mrazek Michaela Drahosova Lukas Sekanina Faculty of Information Technology Brno University of Technology Brno Czech Republic

Taking levodopa, a drug used to treat symptoms of Parkinson’s disease, is often connected with severe side effects, known as Levodopa-induced dyskinesia (LID). It can fluctuate in severity throughout the day and thus is difficult to classify during a short period of a physician’s visit. A low-power wearable classifier enabling long-term and continuous LID classification would thus significantly help with LID detection and dosage adjustment. this paper deals with an automated design of energy-efficient hardware accelerators of LID classifiers that can be implemented in wearable devices. the accelerator consists of a feature extractor and a classification circuit co-designed using genetic programming (GP). We also introduce and evaluate a fast and accurate energy consumption estimation method for the target architecture of considered classifiers. In a multiobjective design scenario, GP evolves solutions showing the best trade-offs between accuracy and energy. Compared to the state-of-the-art solutions, the proposed method leads to classifiers showing a comparable accuracy while the energy consumption is reduced by 49 %.

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River: Sneak Path Aware READ-based In-Memory Computing for 1T1M Memristive Crossbars

River: Sneak Path Aware READ-based In-Memory Computing for 1...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Till Schnittka Chandan Kumar Jha Sallar Ahmadi-Pour Rolf Drechsler University of Bremen Bremen Germany DFKI GmbH Bremen Germany

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

In-memory Computing (IMC) using emerging devices has shown immense potential. Among these devices, memristors have emerged as one of the most popular for performing digital IMC. While several methods exist for digital IMC using memristors, most require expensive write operations in terms of energy, latency, and endurance. Hence, READ-based IMC techniques have been proposed to reduce the number of writes to the memristor crossbar. However, existing techniques rely on simple gates that can be mapped to the memristive crossbar, making them non-optimal, and they suffer from unwanted sneak paths causing undesired behavior. In this work, we alleviate these limitations and propose an optimized synthesis methodology for 1T1M crossbars called RIVER. RIVER supports more complex gates and is sneak-path aware. When comparing RIVER with the state-of-the-art using ISCAS’ 85 and EPFL benchmarks, we achieve 33% less gate utilization on average while reducing the average staircase length by 37%. Moreover, these enhancements result in a 58% reduction in the required crossbar area. After eliminating sneak paths, RIVER still shows 38% less area usage on average as compared to the state-of-the-art.

关键词： Performance evaluation Memristors Logic gates Benchmark testing In-memory computing Rivers electronic circuits

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Split-Et-Impera: A Framework for the design of Distributed Deep Learning Applications

Split-Et-Impera: A Framework for the Design of Distributed D...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Luigi Capogrosso Federico Cunico Michele Lora Marco Cristani Franco Fummi Davide Quaglia Department of Computer Science University of Verona Italy

Many recent pattern recognition applications rely on complex distributed architectures in which sensing and computational nodes interact together through a communication network. Deep neural networks (DNNs) play an important role in this scenario, furnishing powerful decision mechanisms, at the price of a high computational effort. Consequently, powerful state-of-the-art DNNs are frequently split over various computational nodes, e.g., a first part stays on an embedded device and the rest on a server. Deciding where to split a DNN is a challenge in itself, making the design of deep learning applications even more complicated. therefore, we propose Split-Et-Impera, a novel and practical framework that i) determines the set of the best-split points of a neural network based on deep network interpretability principles without performing a tedious try-and-test approach, ii) performs a communication-aware simulation for the rapid evaluation of different neural network rearrangements, and iii) suggests the best match between the quality of service requirements of the application and the performance in terms of accuracy and latency time.

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