检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

116 篇 会议
3 篇 期刊文献

馆藏范围

119 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

106 篇 工学
- 60 篇 控制科学与工程
- 45 篇 计算机科学与技术...
- 26 篇 电气工程
- 11 篇 软件工程
- 9 篇 电子科学与技术（可...
- 3 篇 建筑学
- 3 篇 土木工程
- 2 篇 机械工程
- 2 篇 信息与通信工程
- 1 篇 仪器科学与技术
- 1 篇 化学工程与技术
- 1 篇 石油与天然气工程
- 1 篇 生物医学工程（可授...
- 1 篇 安全科学与工程
7 篇 理学
- 5 篇 数学
- 3 篇 系统科学
- 1 篇 统计学（可授理学、...
5 篇 管理学
- 4 篇 管理科学与工程(可...
- 1 篇 图书情报与档案管...
1 篇 医学
- 1 篇 基础医学(可授医学...

主题

31 篇 embedded systems
15 篇 field programmab...
12 篇 field programmab...
6 篇 programmable log...
6 篇 hardware
6 篇 fpga
5 篇 real-time system...
4 篇 microprocessors ...
3 篇 model predictive...
3 篇 field programmab...
3 篇 computer archite...
3 篇 wireless communi...
3 篇 embedded system
2 篇 data communicati...
2 篇 performance
2 篇 wireless systems
2 篇 co-design
2 篇 heterogeneous (h...
2 篇 parallelism
2 篇 tri-axial accele...

机构

3 篇 bialystok tech u...
3 篇 silesian tech un...
2 篇 vsb tech univ os...
2 篇 univ washington ...
2 篇 institute of mic...
2 篇 kaon syst inc bo...
2 篇 agh univ sci & t...
2 篇 vsb tech univ os...
2 篇 warsaw univ tech...
2 篇 robert bosch gmb...
2 篇 univ washington ...
2 篇 dream chip techn...
2 篇 warsaw univ tech...
1 篇 fraunhofer iosb-...
1 篇 kielce univ tech...
1 篇 dipartimento di ...
1 篇 natl tech univ a...
1 篇 beijing smartchi...
1 篇 scientific resea...
1 篇 univ southampton...

作者

4 篇 konecny jaromir
4 篇 prauzek michal
3 篇 koziorek jiri
3 篇 sikora axel
3 篇 malcher andrzej
3 篇 chmiel miroslaw
3 篇 milik adam
2 篇 jokic dejan
2 篇 bradac z.
2 篇 pulka andrzej
2 篇 liu h
2 篇 hlavica jakub
2 篇 shen my
2 篇 wcislik m.
2 篇 chmiel m.
2 篇 xing gb
2 篇 fisher c
2 篇 beikirch helmut
2 篇 janczak dariusz
2 篇 szydlo tomasz

语言

118 篇 英文
1 篇 中文

检索条件"任意字段=13th IFAC and IEEE Conference on Programmable Devices and Embedded Systems"

共 119 条记录，以下是101-110 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Parallel RF Power Amplifiers Temperature Monitoring System Based on FPGA Device

Parallel RF Power Amplifiers Temperature Monitoring System B...

引用

15th ifac/ieee conference on programmable devices and embedded systems (PDeS)

作者： Wojtkowski, Wojciech Zankiewicz, Andrzej Bialystok Tech Univ Fac Elect Engn Wiejska 45D PL-15351 Bialystok Poland

the paper describes FPGA based temperature measurement system, for parallel monitoring of temperatures of the power semiconductors devices in RF power amplifiers. Proposed system allows for fast detection of the asymmetry in parallel RF power amplifier caused by failure of a single semiconductor power device like CMOS or MOSFET high power transistor. this information is important for evaluation of the system efficiency, current flow symmetry, and allowable output power in a given RF amplifier configuration. the article presents original concept of reading measurements from many 1-wire temperature sensors with minimal time delay between individual measurements thanks to digital temperature sensors operating on separate serial 1-Wire buses. FPGA device collects data from the temperature sensors and sends them through wireless interface to a remote terminal. the structure of the system as well as particular devices are described in the paper. the paper also presents selected results of practical experiments performed to confirm that the assumed concept of using an FPGA device to perform the high simultaneous readings from many sensors is feasible. (C) 2018, ifac (International Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved.

关键词： Digital temperature sensor RF power amplifiers temperature measurement 1-Wire bus semiconductor power devices

来源：评论

学校读者我要写书评

暂无评论

System identification and mathematical modeling of the pandemic spread COVID-19 in Serbia 17th

System identification and mathematical modeling of the pande...

引用

17th ifac conference on programmable devices and embedded systems (PDES)

作者： Sajic, Jasmina Lozanovic Langthaler, Sonja Schroettner, Joerg Baumgartner, Christian Graz Univ Technol Inst Hlth Care Engn European Testing Ctr Med Devices Graz Austria Univ Belgrade Innovat Ctr Fac Mech Engn Kraljice Marije 16 Belgrade Serbia

this paper presents applications of control system theory in biomedical engineering. these methodologies are used in engineering sciences to obtain a mathematical model of systems, but system identification as scientific methodology is rarely used in biomedical engineering. the paper presents exemplarily control theory and system identification as methods for obtaining a mathematical model of the spread SARS-CoV-2 virus. the models obtained in the course of this are data-driven and strongly data-dependent. the available dataset allowed us to consider a model of a pandemic spread in the context of both the number of tested individuals and the number of infected individuals and with a resultant model that is nonlinear. We also considered a mathematical model for the dependence between the number of confirmed infected individuals and the number of deaths caused by the disease. the resulting model is linear given with the transfer function corresponding to the second-order differential equation. the mathematical models developed were additionally analyzed in accordance with controllability and observability.

关键词： biomedical engineering system identification mathematical model covid-19

来源：评论

学校读者我要写书评

暂无评论

Mapping of PRP/HSR redundancy protocols onto a configurable FPGA/CPU based architecture

Mapping of PRP/HSR redundancy protocols onto a configurable ...

引用

2013 13th International conference on embedded Computer systems: Architectures, Modeling and Simulation, IC-SAMOS 2013

作者： Flatt, Holger Jasperneite, Jürgen Dennstedt, Daniel Hung, Tran Dinh Fraunhofer IOSB-INA Application Center Industrial Automation Langenbruch 6 332657 Lemgo Germany Yacoub Automation GmbH Gustav Meyer Allee 25 13355 Berlin Germany

ISBN: (纸本)9781479901036

this paper presents the mapping of the seamless redundancy protocols PRP and HSR in combination with ieee 1588 based clock synchronization onto a configurable CPU/FPGA based Redundancy Box architecture. Whereas core functions of PRP, HSR, and ieee 1588 are mapped onto the FPGA, a CPU executes the control parts of these protocols. An optional attached standard switch ASIC provides direct connection to several network devices. For validation purpose, a special embedded platform is proposed that is composed of an FPGA and a commercial off-the-shelf switch ASIC. the results show that even a low-cost Altera Cyclone IV FPGA comprising 74,000 logic elements fulfills the requirements for protocol processing at 100 Mbps per port. Minimum size frames are forwarded by the FPGA up to two times faster than competitive implementations. three connected PRP/HSR RedBoxes and an ieee 1588 clock master are synchronizing in laboratory within an accuracy of 30 ns. Using several RedBoxes in PRP and HSR mode, a seamless redundancy is demonstrated for a PROFINET RT test network and supplemental network components. Overall, the presented RedBox can be flexibly integrated into time-synchronized industrial networks in order to significantly increase the communication reliability. © 2013 ieee.

关键词： Field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

A Concept for a Cloud-Driven Controller for Wireless Sensors in IoT devices 17th

A Concept for a Cloud-Driven Controller for Wireless Sensors...

引用

17th ifac conference on programmable devices and embedded systems (PDES)

作者： Gaiova, Karolina Prauzek, Michal Konecny, Jaromir Borova, Monika VSB Tech Univ Ostrava Dept Cybernet & Biomed Engn Ostrava Czech Republic

the paper presents an optimization algorithm applied to a cloud-driven controller for wireless sensors in Internet of things (IoT) devices. the experiment investigates operational duty cycle control and energy management of a wireless sensor node device powered by prediction from global solar irradiance in the environment. Rapid increases in the development and growth of smart technologies is placing greater demands on optimizing computing power. the study attempted to manage and optimize wireless terminals using methods to adjust work cycles and planning. the study's contribution is a simulated wireless environmental IoT sensor node and cloud controller implemented in Matlab. the simulation examined energy management and optimization, supplemented by prediction from data measured at different locations in the period 2016-2019. the experiment investigated suitable modes of operation of the device according to data updates in the cloud. the controller was based on the following parameters: state of energy storage, number of failures relative to correctly performed device cycles, and predicted values for charging energy storage from the cloud.

关键词： WSN IoT optimization energy management cloud driven algorithm cloud computing wireless sensor node

来源：评论

学校读者我要写书评

暂无评论

N2V2PRO: Neural Network Mapping Framework for a Custom Vector Processor Architecture 13

N2V2PRO: Neural Network Mapping Framework for a Custom Vecto...

引用

13th ieee International conference on Consumer Electronics - Berlin, ICCE-Berlin 2023

作者： Gesper, Sven thieu, Gia Bao Kohler, Daniel Kock, Markus Berthold, Tim Renke, Oliver Blume, Holger Paya-Vaya, Guillermo Technische Universität Chair for Chip Design for Embedded Computing Braunschweig Germany Robert Bosch GmbH Germany Dream Chip Technologies GmbH Germany Institute of Microelectronic Systems Leibniz Universität Hannover Germany

ISBN: (纸本)9798350324150

Convolutional neural networks (CNNs) have been demonstrated to be a successful approach in the field of artificial intelligence (AI). Deploying CNNs on embedded devices at a large scale would contribute significantly to the advancement and practical implementation of AI in various industries. However, the complexity of CNNs in terms of memory and operation requirements poses challenges in terms of computing performance, memory bandwidth, and flexibility of the executing hardware. this paper introduces a framework that addresses these issues through model quantization and hardware acceleration on a scalable vertical vector processor architecture. Firstly, the framework includes a method for layer fusion, which is designed to optimize the hardware utilization. Secondly, data storage is optimized to enhance memory efficiency. Lastly, CNNs are mapped onto the vertical vector processing concept of the hardware accelerator. the effectiveness of the proposed framework is evaluated by analyzing the accelerator efficiency based on a field-programmable gate array (FPGA). the results demonstrate that the framework offers flexibility, configurability, and efficient mapping for typical CNN implementations. the framework achieves up to 84% of the peak performance of the vector processor for the VGG net. © 2023 ieee.

关键词： Mapping

来源：评论

学校读者我要写书评

暂无评论

Hardware design of a neural processing unit for bio-inspired computing

Hardware design of a neural processing unit for bio-inspired...

引用

Annual ieee Northeast Workshop on Circuits and systems (NEWCAS)

作者： Laurent Fiack Laurent Rodriguez Benoît Miramond UMR 8051 ETIS Lab Cergy-Pontoise France

Unsupervised artificial neural networks are now considered as a likely alternative to classical computing models in many application domains. For example, recent neural models defined by neuro-scientists exhibit interesting properties for an execution in embedded and autonomous systems: distributed computing, unsupervised learning, self-adaptation, self-organisation, tolerance. But these properties only emerge from large scale and fully connected neural maps that result in intensive computation coupled with high synaptic communications. We are interested in deploying these powerful models in the embedded context of an autonomous bio-inspired robot learning its environment in realtime. So we study in this paper in what extent these complex models can be simplified and deployed in hardware accelerators compatible with an embedded integration. thus we propose a Neural Processing Unit designed as a programmable accelerator implementing recent equations close to self-organizing maps and neural fields. the proposed architecture is validated on FPGA devices and compared to state of the art solutions. the trade-off proposed by this dedicated but programmable neural processing unit allows to achieve significant improvements and makes our architecture adapted to many embedded systems.

关键词： Hardware Neurons Adaptation models Computational modeling Biological system modeling Computer architecture Field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Implementing an OFDM receiver on the RaPiD reconfigurable architecture

Implementing an OFDM receiver on the RaPiD reconfigurable ar...

引用

13th International conference on Field-programmable Logic and Applications (FPL 2003)

作者： Ebeling, C Fisher, C Xing, GB Shen, MY Liu, H Univ Washington Dept Comp Sci & Engn Seattle WA 98195 USA Kaon Syst Inc Bothell WA 98201 USA Univ Washington Dept Elect Engn Seattle WA 98195 USA

ISBN: (纸本)3540408223

Field-programmable gate arrays (FPGAs) have become an extremely popular implementation technology for custom hardware because they offer a combination of low cost and very fast turnaround. Because of their in-system reconfigurability, FPGAs have also been suggested as an efficient replacement for application-specific integrated circuits (ASICs) and digital signal processors (DSPs) for applications that require a combination of high performance, low cost, and flexibility. Unfortunately, the use of FPGAs in mobile embedded systems platforms is hampered by the very large overhead of FPGA-based architectures. Coarse-grained configurable architectures can reduce this overhead substantially by taking advantage of the application domain to specialize the reconfigurable architecture via coarse-grained components and interconnects. this paper presents the design and implementation of an OFDM receiver in the RaPiD reconfigurable architecture as a case study for comparing the relative cost and performance of ASIC, DSP, FPGA, and coarse-grained reconfigurable architectures. RaPiD is a coarse-grained reconfigurable architecture specialized to the domain of signal and image processing. the RaPiD architecture provides a reconfigurable pipelined datapath controlled by efficient reconfigurable control logic. We have implemented the computationally intensive parts of an OFDM receiver on the RaPiD architecture and have developed careful estimates of corresponding implementations in representative ASIC, DSP and FPGA technology. Our results show that, for this application, RaPiD fills the cost/performance gap between programmable DSP and ASIC architectures, achieving a factor of 6 better than a DSP implementation but a factor of 6 less than an ASIC implementation.

关键词： data communications devices wireless systems adaptable architectures heterogeneous (hybrid) systems special-purpose and application-based systems application studies resulting in better multiple-processor systems reconfigurable hardware signal processing systems design studies

来源：评论

学校读者我要写书评

暂无评论

embedded approach for edge recognition: Case study: Vehicle registration plate recognition

Embedded approach for edge recognition: Case study: Vehicle ...

引用

ieee SSD International Multi-conference on systems, Signals and devices

作者： Safa Issaoui Ridha Ejbeli Tarek Frikha Mohamed Abid ISIMG Higher Institute of computer Sciences and Multimedia of Gabes Gabes Tunisia CES Lab National Engineering School of Sfax Sfax Tunisia Sfax University National Engineering School of Sfax Sfax Tunisia

ISBN: (纸本)9781509012923

the development of multimedia embedded applications continues to increase. As an example, image recognition applications are not only developed for the PCs but also for the embedded systems such as the face recognition, the texture detection and the edge detection. In this paper, we will present a hardware architecture based on an adaptation approach. To validate this architecture, an edge detection approach is chosen. To illustrate the proposed approach, vehicle registration plate recognition is proposed. the latter application was tested in a first time by a software implementation. n a second time, we use the co design technique based on a mixed Hardware Software architecture. the used platform for the implementation is the Xilinx ML 507 FPGA platform.

关键词： Decision support systems Image edge detection Vehicles Hardware Computer architecture Software Field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Block-parallel programming for real-time embedded applications

Block-parallel programming for real-time embedded applicatio...

引用

International conference on Parallel Processing

作者： Black-Schaffer, David Dally, William J. Department of Information Technology Uppsala University Uppsala Sweden Department of Computer Science Stanford University Palo Alto United States

ISBN: (纸本)9780769541563

embedded media applications have traditionally used custom ASICs to meet their real-time performance requirements. However, the combination of increasing chip design cost and availability of commodity many-core processors is making programmable devices increasingly attractive alternatives. Yet for these processors to be successful in this role, programming systems are needed that can automate the task of mapping the applications to the tens-tohundreds of cores on current and future many-core processors, while simultaneously guaranteeing the real-time throughput constraints. this paper presents a block-parallel program description for embedded real-time media applications and automatic transformations including buffering and parallelization to ensure the program meets the throughput requirements. these transformations are enabled by starting with a high-level, yet intuitive, application description. the description builds on traditional stream programming structures by adding simple control and serialization constructs to enable a greater variety of applications. the result is an application description that provides a balance of flexibility and power to the programmer, while exposing the application structure to the compiler at a high enough level to enable useful transformations without heroic analysis. © 2010 ieee.

关键词： Image processing

来源：评论

学校读者我要写书评

暂无评论

the Janus project: Boosting spin-glass simulations using FPGAs

The Janus project: Boosting spin-glass simulations using FPG...

引用

12th ifac conference on programmable devices and embedded systems, PDeS 2013

作者： Baity-Jesi, M. Baños, R.A. Cruz, A. Fernandez, L.A. Gil-Narvion, J.M. Gordillo-Guerrero, A. Iñiguez, D. Maiorano, A. Mantovani, F. Marinari, E. Martin-Mayor, V. Monforte-Garcia, J. Muñoz Sudupe, A. Navarro, D. Parisi, G. Perez-Gaviro, S. Pivanti, M. Ricci-Tersenghi, F. Ruiz-Lorenzo, J.J. Schifano, S.F. Seoane, B. Tarancon, A. Tripiccione, R. Yllanes, D. Departamento de Física Teórica i Universidad Complutense 28040 Madrid Spain Zaragoza Spain Departamento de Física Teórica Universidad de Zaragoza 50009 Zaragoza Spain Departamento de Ingeniería Eléctrica Electrónica y Automática Universidad de Extremadura 10071 Cáceres Spain Dipartimento di Fisica La Sapienza Università di Roma 00185 Rome Italy Dipartimento di Fisica Università di Ferrara and INFN Sezione di Ferrara Ferrara Italy Departamento de Física Universidad de Extremadura 06071 Badajoz Spain

ISBN: (纸本)9783902823533

Spin-glasses have become one of the most computing-demanding problems of the last 50 years in Statistical Physics. these extremely slow systems represent a clear example of an easy-to-describe but hard-to-simulate numerical problem. We have developed an FPGAs architecture, called Janus, able to exploit the simplicity of the problem by an extensive parallelization of the computing units. In this work we describe the architecture after motivating the problem. We give the performance figures compared with other more usual architectures. We have obtained a clear advantage in terms of computing power which produced several top results in the field. In addition, we describe the current development of the next generation of the infrastructure: Janus II. © ifac.

关键词： Field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共12页 << < 3 4 5 6 7 8 9 10 11 12 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：