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On routing algorithms for the DPillar data centre networks 15th

On routing algorithms for the DPillar data centre networks

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15th international conference on algorithms and architectures for parallel processing, ica3pp 2015

作者： Kiasari, Abbas Eslami Navaridas, Javier Stewart, Iain A. School of Computer Science University of Manchester Oxford Road ManchesterM13 9PL United Kingdom Science Laboratories School of Engineering and Computing Sciences Durham University South Road DurhamDH1 3LE United Kingdom

ISBN: (纸本)9783319271392

the DPillar data centre networks were introduced as an attractive topology for server-centric data centre networks and have recently received considerable attention. In this paper, we first derive analytically, and validate experimentally, the average hop count and the aggregate bottleneck throughput of the DPillar networks with a focus on single-path routing algorithms and the all-to-all traffic pattern. We use these models to explore the design space of the DPillar networks as a case study. In addition, we discuss the limitations of the original routing algorithms, showing that they do not benefit from the rich connectivity provided by the DPillar network and consequently do not tolerate link failures very well. To overcome these limitations we propose a collection of routing algorithms which keep the simplicity of the original but enable a more effective utilisation of the network. We empirically evaluate our proposed routing algorithms and we find that they outperform the original algorithms as regards network throughput (∼ 2x), average hop count (∼ 5% − 10%), load balance and fault tolerance. © Springer international Publishing Switzerland 2015.

关键词： Routing algorithms

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Addressing NoC reliability through an efficient fibonacci-based crosstalk avoidance codec design 15th

Addressing NoC reliability through an efficient fibonacci-ba...

引用

15th international conference on algorithms and architectures for parallel processing, ica3pp 2015

作者： Shirmohammadi, Zahra Miremadi, Seyed Ghassem International Campus Sharif University of Technology Kish Island Iran Department of Computer Engineering Sharif University of Technology Tehran Iran

ISBN: (纸本)9783319271361

the reliable transfer in Network on Chips (NoCs) can be threatened by crosstalk fault occurring in wires. Crossstalk fault is due to inter-wire coupling capacitance that based on the patterns of transitions appearing on the wires, significantly limits the reliability of NoCs. Among these transitions, 101 and 010 bit patterns impose the worst crosstalk effects to wires. this work intends to increase the reliability of NoCs against crosstalk faults by applying an improved Fibonacci-based numeral system, called Doubled-Penultimate Fibonacci (DP-Fibo). In the DP-Fibo coding algorithm, code words without ‘101’ and ‘010’ bit patterns are produced to reduce crosstalk faults. Experimental results show that the proposed numerical system: (1) can be utilized in NoC channels with any arbitrary wire width and, (2) can outperform other existing coding mechanism in providing significant reliability improvement and reduction over the area occupation and power consumption of NoCs. Experiments indicated that DP-Fibo provides improvement in area occupation, power-delay product, critical path and power consumptions of codec with respect to the state-of-the-art Fibonacci coding mechanism by 13%, 22.7%, 5% and 25% respectively. © Springer international Publishing Switzerland 2015.

关键词： Network-on-chip

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Identifying repeated interleavings to improve the efficiency of concurrency bug detection 15th

Identifying repeated interleavings to improve the efficiency...

引用

15th international conference on algorithms and architectures for parallel processing, ica3pp 2015

作者： Wu, Zhendong Lu, Kai Wang, Xiaoping Science and Technology on Parallel and Distributed Processing Laboratory College of Computer National University of Defense Technology Changsha410073 China

ISBN: (纸本)9783319271392

Detecting concurrency bugs is becoming increasingly important. Many pattern-based concurrency bug detectors focus on the specific types of interleavings that are correlated to concurrency bugs. To detect multiple types of concurrency bugs, general detectors focus on multiple types of interleaving patterns, including data race pattern, atomicity violation pattern, and atomic-set violation pattern. Unfortunately, they suffer from redundant analysis due to repeated interleavings, which may affect the efficiency of concurrency bug detection. Hence, we propose an approach to identify the repeated interleavings. To the best of our knowledge, this is the first approach that can prune repeated interleavings to improve the efficiency of concurrency bug detection. We apply our approach to existing general detectors (PECAN and Maple) to avoid analyzing repeated interleavings. We evaluated the general detectors with and without our approach, respectively. the experimental results show that the bug detection results are not affected. With our approach, the bug detection time of PECAN and Maple are reduced by 40.0% and 44.4%, respectively. Additionally, our approach does not affect the overhead of bug detection, and consumes only a little memory. © Springer international Publishing Switzerland 2015.

关键词： Efficiency

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DFIS: A scalable distributed fingerprint identification system 15th

DFIS: A scalable distributed fingerprint identification syst...

引用

15th international conference on algorithms and architectures for parallel processing, ica3pp 2015

作者： Zhao, Yunxiang Zhang, Wanxin Li, Dongsheng Huang, Zhen National Laboratory for Parallel and Distributed Processing College of Computer National University of Defence Technology ChangshaHunan410073 China

ISBN: (纸本)9783319271361

Fingerprint has been widely used in a variety of biometric identification systems. However, with the rapid development of fingerprint identification systems, the amount of fingerprints information stored in systems has been rising sharply, making it challenging to process and store fingerprints efficiently and robustly with traditional standalone systems and relational databases. In this paper, we propose a scalable distributed fingerprint identification system, named DFIS. It combines the feature extraction procedure with HIPI library and optimizes the load balance strategy of MongoDB to construct a much more robust and stable system. Related experiments and simulations have been carried out and results show that DFIS can reduce the time expense by 70% during the features extraction procedural. For load balance of MongoDB, DFIS can decrease the difference of access load to less than 5% and meanwhile decrease 50% data migration to gain more reasonable distribution of operation load and data load among shards compared with the default load balance strategy in MongoDB. © Springer international Publishing Switzerland 2015.

关键词： Distributed computer systems

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parallel aware hybrid Solid-State storage 15th

Parallel aware hybrid Solid-State storage

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15th international conference on algorithms and architectures for parallel processing, ica3pp 2015

作者： He, Dan Wang, Fang Feng, Dan Liu, Jingning Wu, Yunxiang He, Ying Hu, Yang Wuhan National Laboratory for Optoelectronics School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China Nanchang Hangkong University Nanchang330063 China China Ship Development and Design Center Wuhan430064 China

ISBN: (纸本)9783319271392

Compared with tradition disk, NAND Flash has advantages of higher performance and shock resistance. But before write, NAND Flash must erase the old messages. that why NAND Flash based Solid State Disks (SSDs) always use the log-based schemes to improve the performance. Compared with NAND Flash, Phase Change Memory (PCM) has higher write performance, longer lifetime, and can update in-place, but its cost is high and capacity is low. So, in PCM and NAND Flash hybrid SSD, PCM is always used as log region, such as In-Page Logging-based (hybrid-IPL) SSD. the log-based SSD incurs a large number of merge operations. the cost of merge operation is very high because it involves many read, write operations, as well as an erase operation. So, how to reduce the cost of merge operations is the critical challenge to log-based hybrid (PCM and flash) SSD. In this paper, we propose a new merge scheme in PCM and NAND Flash hybrid SSD, called parallel aware hybrid In-Page Logging-based (P-aware-IPL) SSD. this scheme can exploit the die-level and plane-level parallelism of flash. Leveraging these two levels of parallelism, the cost of full merge is significantly reduced compared with that of hybrid-IPL SSD scheme and there is no other additional overhead in our algorithm. Experiment results have shown that the proposed P-aware-IPL reduces the flash write and erase operations by up to 10% and average response time by up to 22% against the hybrid-IPL scheme. © Springer international Publishing Switzerland 2015.

关键词： Cost reduction

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