In SoCs (System-on-Chip) with mixed-signal cores, boththe functional behavior and the production tests should be simulated at top level before tape-out. the use of behavioral models for the analog and mixed-signal co...
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In SoCs (System-on-Chip) with mixed-signal cores, boththe functional behavior and the production tests should be simulated at top level before tape-out. the use of behavioral models for the analog and mixed-signal cores enables simulation of the whole signal path including the analog inputs or outputs of the mixed-signal cores. Since many SoCs are described in the Verilog HDL (Hardware Description Language) and since Verilog does not permit analog values on wires, the analog values have to be converted into high-speed serial binary data streams. this requires a virtual serial interface, which is described in this paper. the interface has been extended to enable the simulation with analog as well as digital signals, equivalent to the use of analog and digital tester channels.
Software product lines (PLs) are large, complex systems, demanding high maintainability and enhanced flexibility. Nonetheless, in the state of the art PL methods, features are scattered and tangled throughout the syst...
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Software product lines (PLs) are large, complex systems, demanding high maintainability and enhanced flexibility. Nonetheless, in the state of the art PL methods, features are scattered and tangled throughout the system components, leading to poor maintainability. Additionally, the majority of PL methods support manual product composition, while the implementation of feature-level variability in PL products influences the system's conceptual integrity. Generative programming techniques do enhance flexibility, but on the cost of maintainability. the feature-architecture mapping (FArM) method provides a stronger mapping between features and the architecture. It is based on a series of transformations on the initial PL feature model. During these transformations, architectural components are derived, encapsulating the business logic of each transformed feature and having interfaces reflecting the feature interactions. the flexibility of FArM architectures is supported through the explicit integration of plug-in mechanisms. the methodology is evaluated in the context of a wireless handheld device PL
Advances in IC fabrication technology have made the design of complex and powerful embedded appliances feasible. To design such appliances, a hardware/software co-design methodology, which allows concurrent hardware a...
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Advances in IC fabrication technology have made the design of complex and powerful embedded appliances feasible. To design such appliances, a hardware/software co-design methodology, which allows concurrent hardware and software development before a system prototype is available, is the preferred solution. this paper presents a co-design methodology for embedded DSP applications, starting from MATLAB/Simulink descriptions and exploring the design space based on SystemC 2.1. It unifies software (applications and RTOS) and hardware (CPU, DSP and glue logic) through different abstraction levels. the paper presents the different entities, tools and techniques required for an accurate system co-simulation during all refinement phases, from functionality to implementation.
Using the constraint-based modeling approach, we have developed a diagnostic component, which is able to identify errors made by learners of a logicprogramming language when implementing a given task specification. I...
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the proceedings contain 24 papers from the inductivelogicprogramming - 13thinternationalconference, ILP 2003. the topics discussed include: complexity parameters for first-order classes;applying theory revision to...
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the proceedings contain 24 papers from the inductivelogicprogramming - 13thinternationalconference, ILP 2003. the topics discussed include: complexity parameters for first-order classes;applying theory revision to the design of distributed databases;ILP for mathematical discovery;efficient data structures for inductivelogicprogramming;graph kernels and gaussian processes for relational reinforcement learning and on condensation of a clause.
We applied the constraint-based approach to develop a web-based diagnosis system for Prolog. this paper introduces the evaluation results which reflects the current efficacy of our system. We gathered 261 log files wh...
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We formalized the DE2 hierarchical, occurrence-oriented finite state machine (FSM) language, and have developed a proof theory allowing the mechanical verification of PSM descriptions. Using the ACL2 functional logic,...
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this paper introduces rule-based reasoning (RBR) Expert System for network fault and security diagnosis and a mechanism for optimization. In this system, we use agent collaboration mechanism which is the process that ...
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