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检索条件"任意字段=13th International Conference on Inductive Logic Programming"

共 344 条记录，以下是321-330 订阅

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A Predictable Transactional Memory Architecture with Selective Conflict Resolution for Mixed-Criticality Support in MPSoCs

A Predictable Transactional Memory Architecture with Selecti...

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IEEE/IFIP international conference on Embedded and Ubiquitous Computing, EUC

作者： Zaher Owda Roman Obermaisser University of Siegen Germany

Transactional memories can radically simplify the programming of mixed-criticality systems by offering atomicity, consistency and isolation guarantees between subsystems of different criticality. A major objective in mixed-criticality systems is a modular safety case where each subsystem is certified to the respective safety assurance level. the prerequisite for this modular certification is the prevention of any effect of low criticality subsystems on the temporal behavior of subsystems of higher criticality. this paper introduces a transactional memory architecture based on a time-triggered network-on-a-chip with fault isolation based on a TDMA scheme. the memory architecture contains a memory gateway for selective conflict resolution when committing transactions. the memory gateway triggers a rollback of a transaction in case higher criticality subsystems would be affected. the proposed transactional memory architecture ensures that the validation and certification of high criticality subsystems does not depend on subsystems with lower criticality.

关键词： logic gates Real-time systems Embedded systems Hardware Memory architecture Schedules Systems architecture

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OOFM - A feature modeling approach to implement MPLs and DSPLs

OOFM - A feature modeling approach to implement MPLs and DSP...

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IEEE international conference on Information Reuse and Integration (IRI)

作者： Victor Travassos Sarinho Antônio L. Apolinário Eduardo S. de Almeida UEFS-DEXA Feira de Santana Bahia Brazil UEFS-DEXA Av. Transnordestina S/N Feira de Santana-BA UFBA-IM Salvador Bahia Brazil UFBA-IM Av. Adhemar de Barros S/N Campus Ondina Salvador Bahia UFBA RiSE Av. Adhemar de Barros S/N Campus Ondina Salvador Bahia

this paper uses the Object Oriented Feature Modeling (OOFM) technique to develop Multiple Product Lines (MPLs) and Dynamic SPLs (DSPLs). the idea is combine defined OOFM resources in a Model-View-Controller (MVC) architectural style. As result, a pattern-based Product Line Architecture (PLA) is provided, a kind of middleware that performs an advanced usage of multiple and dynamic OOFM features able to generate desired MPLs and DSPLs.

关键词： Object oriented modeling Software Multiprotocol label switching Adaptation models Programmable logic arrays programming Observers

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Task oriented software understanding

Task oriented software understanding

引用

IEEE international conference on Automated Software Engineering (ASE)

作者： A. Erdem W.L. Johnson S. Marsella Computer Science Department USC Information Sciences Institute Marina del Rey CA USA

the main factors that affect software understanding are the complexity of the problem solved by the program, the program text, the user's mental ability and experience and the task being performed. the paper describes a planning approach solution to the software understanding problem that focuses on the user's task and expertise. First, user questions about software artifacts have been studied and the most commonly asked questions are identified. these questions are organized into a question model and procedures for answering them are developed. then, the patterns in user questions while performing certain tasks have been studied and these patterns are used to build generic task models. the explanation system uses these task models in several ways. the task model, along with a user model, is used to generate explanations tailored to the user's task and expertise. In addition, the task model allows the system to provide explicit task support in its interface.

关键词： Documentation Software maintenance Software performance logic programming Computer science Computer industry Writing Code standards Automatic programming Humans

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Surface potential compact model for embedded flash devices oriented to IC memory design

Surface potential compact model for embedded flash devices o...

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international conference on Ultimate Integration of Silicon, ULIS

作者： Davide Garetto Denis Rideau Fabien Gilibert Alexandre Schmid Hervé Jaouen Yusuf Leblebici IBM Systems and Technology Group Crolles France Ecole Polytechnique Fédérale de Lausanne Lausanne Switzerland STMicroelectronics Crolles France

A surface potential-based model for embedded flash memory cells has been developed with the purpose of providing a comprehensive physical understanding of the device operation suitable for performance optimization in memory circuit design. An accurate validation methodology takes into account charge balance effects on the isolated floating gate node and parasitic couplings inside and between the memory cells. the compact model supports DC, AC and transient analyses, including program/erase bias scalability, drain disturb and memory endurance degradation models due to oxide aging. After validation, the model has been applied to parametric analysis and used to evaluate critical trade-offs in memory design.

关键词： logic gates Integrated circuit modeling Analytical models programming Transient analysis Voltage measurement Ash

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Probabilistic neuromorphic system using binary phase-change memory (PCM) synapses: Detailed power consumption analysis

Probabilistic neuromorphic system using binary phase-change ...

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IEEE conference on Nanotechnology

作者： Daniele Garbin Manan Suri Olivier Bichler Damien Querlioz Christian Gamrat Barbara DeSalvo CEA-LETI-MINATEC Grenoble France CEA-LIST France IEF-Paris Orsay France CEA-LETIMINATEC 38054 Grenoble France

In this paper we investigate the use of phase-change memory (PCM) devices as binary probabilistic synapses in a neuromorphic computing system for complex visual pattern extraction. Different PCM programming schemes for architectures with- or without-selector devices are provided. the functionality of the system is tested through large-scale neural network simulations. the system-level simulations show that such a system can solve a complex real-life video processing problem (vehicle counting) with high recognition rate (>94%) and low power consumption. the impact of the resistance window on the power consumption of the system is also studied. Results show that the learning-mode power consumption can be dramatically reduced if the RESET state of the PCM devices is tuned to a relatively low resistance. Read-mode power consumption, on the other hand, can be minimized by increasing the resistance values for both SET and RESET states of the PCM devices.

关键词： Phase change materials Neurons programming Power demand Computer architecture Probabilistic logic Resistance

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Objective functions for falsification of signal temporal logic properties in cyber-physical systems

Objective functions for falsification of signal temporal log...

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IEEE international conference on Automation Science and Engineering (CASE)

作者： Johan Eddeland Sajed Miremadi Martin Fabian Knut Åkesson Institution of Electrical Engineering Chalmers University of Technology Gothenburg Sweden Volvo Car Corporation Gothenburg Sweden

Cyber-physical systems, such as automation and automotive systems, are highly complex systems that are frequently also safety-critical. thus, it is important that these systems behave as intended, as incorrectness can have serious consequences. Due to continuous dynamics that yield infinite state spaces, the systems cannot be exhaustively tested to guarantee correct behavior, but systematic testing can be used to systematically search for behavior that is inconsistent with the requirements. However, manual testing is a tedious and error-prone task, and thus it is desirable to automate as much of the testing process as possible to increase efficiency and eliminate manual errors. this paper considers falsification of requirements expressed as temporal logic formulae to find errors in the Model-in-the-Loop stage of model-based development. the falsification is an optimization procedure where the objective function is determined by the definition of a quantitative semantics for the temporal logic formalism, and the optimization is performed over an input parametrization. It is shown that in certain cases where the discreteness of the system under test manifests itself in the objective function, the robustness values for the temporal logic specifications need to be modified. this paper presents two alternative objective functions suitable for these cases, and illustrates their use with both a small example and a use case from Volvo Car Corporation.

关键词： Linear programming Optimization Robustness Testing Safety Cyber-physical systems Semantics

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Balance control by diffuse logic for a phoenix hexapod robot

Balance control by diffuse logic for a phoenix hexapod robot

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international conference on Fuzzy Systems and Knowledge Discovery (FSKD)

作者： Darwin Alulema Cristian Andino Diego Rodríguez Víctor Proaño Alexander Ibarra Derlin Morocho Freddy Tapia Verónica Alulema Departamento de Eléctrica y Electrónica Universidad de las Fuerzas Armadas ESPE Sangolqui Ecuador Departamento de Ciencias de la Computación Universidad de las Fuerzas Armadas ESPE Sangolqui Ecuador

Using diffuse control algorithms, a position control for the six extremities of the Hexapod Robot was built. As input to the controller, a LIS3DSH accelerometer was used, which gives the Roll values for the angle in which the accelerometer tilts, typical of the Discovery STM32F4 card. It was necessary to build a PI controller in order to reduce the error in stationary state and stabilize the robot in a zero degree tilt position, allowing the Hexapod robot to stand and balance automatically over different surfaces.

关键词： Servomotors Accelerometers thigh Robot sensing systems programming

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Designing and programming “Gameland” web portal focusing on serious games

Designing and programming “Gameland” web portal focusing o...

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international conference on Emerging eLearning Technologies and Applications (ICETA)

作者： M. Hosťovecký L. Lipovský D. Tóthová University of Ss. Cyril and Methodius / Department of Applied Informatics and Math Trnava Slovakia University of Ss. Cyril and Methodius/Department of Applied Informatics and Math Trnava Slovakia Slovak University of Agricultural in Nitra/Centre of Information Technologies Nitra Slovakia

the main purpose of the present paper was to design and develop a web portal that would store intelligent educational games aiming to eliminate cognitive shortcomings in elementary and secondary school pupils. the design of the portal was based on a previously implemented project that was aiming to find out the differences in cognitive levels among elementary and secondary school pupils in five selected subjects. the tests were carried out on a sample of pupils in the border region between Slovakia and the Czech Republic. the evaluation of these tests revealed specific shortcomings in specific cases. On this basis, we decided to create so-called serious games. For the purpose of storing these games it was necessary to create a portal that would contain them.

关键词： Portals Games Databases Electronic mail logic gates Navigation Education

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A generic query-translation framework for a mediator architecture

A generic query-translation framework for a mediator archite...

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international conference on Data Engineering

作者： J. Calmet S. Jekutsch J. Schu Department of Computer Science Institute for Algorithms and Cognitive Systems University of Karlsruhe Germany

A mediator is a domain-specific tool to support uniform access to multiple heterogeneous information sources and to abstract and combine data from different but related databases to gain new information. this middleware product is urgently needed for these frequently occurring tasks in a decision support environment. In order to provide a front end, a mediator usually defines a new language. If an application or a user submits a question to the mediator, it has to be decomposed into several queries to the underlying information sources. Since these sources can only be accessed using their own query language, a query translator is needed. this paper presents a new approach for implementing query translators. It supports conjunctive queries as well as negation. Care is taken to enable information sources of which processing capabilities do not allow conjunctive queries in general. Rapid implementation is guided by reusing previously prepared code. the specification of the translator is done declaratively and domain-independently.

关键词： Database languages logic programming Computer architecture Computer science Decision support systems Data engineering Web sites Application software Mediation Gratings

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Verification of a combinational loop based arbitration scheme in a system-on-chip integration architecture

Verification of a combinational loop based arbitration schem...

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international conference on VLSI Design

作者： Y. Xia P. Ashar C CRL NEC-USA Inc. Princeton NJ USA

We tackle the problem of verifying correctness properties on an HDL implementation of a system-on-chip bus-based integration architecture. the bus architecture is characterized by a 2-level arbitration scheme and the absence of a centralized controller. Checking correctness properties on an implementation can be hard because it is common for an implementation to contain constructs which are difficult to capture using a synchronous FSM model. the hard part in our case is that for performance reasons the second-level arbitration is based on a token-ring protocol implemented as a novel combinational loop. While the combinational loop is non-inverting, there is no acyclic implementation which can mimic its functionality. Our contribution has been to show how the combinational loop, and hence the arbitration scheme, can be modeled by means of mechanical transformations of the implementation model. We model check a 4-client base case implementation followed by an inductive argument for the correctness of an n-client implementation. Our approach including the combinational loop modeling and the inductive proof technique has general application to other similar protocols. Our verification methodology involved checking a Verilog implementation for desired properties using symbolic model checking in the VIS system from UC Berkeley. Checking properties on the base case required negligible amount of CPU resources. While there have been a number of formal verification case studies, we do not believe that any previous work has proposed a general purpose technique for modeling combinational loops.

关键词： System-on-a-chip Protocols Backplanes Hardware design languages Silicon Centralized control logic Delay Computer architecture National electric code

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