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检索条件"任意字段=13th International Conference on Parallel Architecture and Compilation Techniques"

共 495 条记录，以下是1-10 订阅

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Proceedings 30th international conference on parallel architectures and compilation techniques [Title page]

Proceedings 30th International Conference on Parallel Archit...

引用

international conference on parallel architecture and compilation techniques (PACT)

Presents the title page of the proceedings record.

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Maximum Power Point Tracking of Series-parallel Connected Bifacial PV Modules 13

Maximum Power Point Tracking of Series-Parallel Connected Bi...

引用

13th international conference on Renewable Energy Research and Applications

作者： Ajmal, Aidha Muhammad Yang, Yongheng Gyawali, Bikash Zhejiang Univ Coll Elect Engn Hangzhou 310058 Peoples R China

ISBN: (纸本)9798350375596;9798350375589

Bifacial photovoltaic (BiPV) modules capture solar energy from their front and rear surfaces, posing unique challenges due to their exposure to non-uniform irradiance and temperature variations. In the pursuit of optimizing the energy output of BiPV systems, this paper focuses on investigating the effectiveness of the maximum power point tracking (MPPT) methods of series-parallel (SP) connected BiPV modules using advanced metaheuristic algorithms like the genetic algorithm (GA), particle swarm optimization (PSO), and gray wolf optimizer (GWO). the efficiency of the selected techniques is compared to each other in tracking the maximum power point (MPP) of a (2 x 2) BiPV array feeding a DC/DC converter under three different cases. through detailed simulations, the results demonstrate that these algorithms can significantly enhance the energy yield of BiPV arrays of SP configurations. the findings indicate that selecting an optimization strategy is essential to increasing the overall effectiveness of BiPV systems. Each methodology provides unique benefits depending on the operating circumstances.

关键词： Bifacial photovoltaic (BiPV) series-parallel configuration MPPT methods bifacial gain PV efficiency

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PARENDI: thousand-Way parallel RTL Simulation 25

PARENDI: Thousand-Way Parallel RTL Simulation

引用

30th international conference on Architectural Support for Programming Languages and Operating Systems-ASPLOS

作者： Emami, Mahyar Bourgeat, thomas Larus, James R. Ecole Polytech Fed Lausanne Lausanne Switzerland

ISBN: (纸本)9798400710797

Hardware development critically depends on cycle-accurate RTL simulation. However, as chip complexity increases, conventional single-threaded simulation becomes impractical due to stagnant single-core performance. PARENDI is an RTL simulator that addresses this challenge by exploiting the abundant fine-grained parallelism inherent in RTL simulation and efficiently mapping it onto the massively parallel Graphcore IPU (Intelligence Processing Unit) architecture. PARENDI scales up to 5888 cores on 4 Graphcore IPU sockets. It allows us to run large RTL designs up to 4x faster than the most powerful state-of-the-art x64 multicore systems. To achieve this performance, we developed new partitioning and compilation techniques and carefully quantified the synchronization, communication, and computation costs of parallel RTL simulation: the paper comprehensively analyzes these factors and details the strategies that PARENDI uses to optimize them.

关键词： Bulk-synchronous parallel RTL Simulation Cycle-accurate Partitioning Submodular Load Balancing

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How to Select Quantum Compilers and Quantum Computers Before compilation 13

How to Select Quantum Compilers and Quantum Computers Before...

引用

13th international conference on Cloud Computing and Services Science (CLOSER)

作者： Salm, Marie Barzen, Johanna Leymann, Frank Wundrack, Philipp Univ Stuttgart Inst Architecture Applicat Syst Univ Str 38 Stuttgart Germany

ISBN: (纸本)9789897586507

Quantum computers might solve specific problems faster than classical computers in the future. But their actual qubit numbers are small, and the error rates are high. However, quantum computers are already used in various areas and a steadily increasing number is made available by cloud providers. To execute a quantum circuit, it is mapped to the quantum computer's hardware. the resulting compiled circuit strongly influences the precision of the execution in terms of occurring errors caused by used qubits and quantum gates. Selecting an optimal one is, therefore, essential. SDKs are used to implement circuits and differ in supported cloud providers and programming languages. these differences complicate a change to other backends. In previous work, we developed an automated framework to translate a given circuit and compile it on available quantum computers using multiple compilers. the compilation results can be prioritized and executed. Nevertheless, the translation and compilation with all compilers and quantum computers is resource-intensive and does not scale well with further backends in the future. We, therefore, present an extension to automatically select suitable compiler and quantum computer combinations based on the user's needs, e.g., for short waiting times and precise results based on past executions. To demonstrate and validate our approach, we show a prototype and case study.

关键词： Quantum Computing NISQ Analyzer Decision Support Machine Learning Prediction

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Low Power Microarchitecture Designs of ACS Block in Viterbi Decoder: A Review 13

Low Power Microarchitecture Designs of ACS Block in Viterbi ...

引用

13th international conference on Information Communication and Management (ICICM)

作者： Mosbeh, Asmaa Ibraheem, Ali A. Y. Mostafa, Hassan Yousef, Khalil Assiut Univ Fac Engn Elect Engn Dept Assiut Egypt Cairo Univ Fac Engn Elect & Commun Dept Cairo Egypt

ISBN: (纸本)9798400708114

Low-power microarchitecture designs of Viterbi decoder are considered one of the on-demanding issues in Very Large-Scale Integration (VLSI). Viterbi decoders consume 35% of the power and 76% of the complexity in digital communication schemes, e.g., IEEE 802.11 a/g WLAN schemes. Development of Viterbi decoder itself reduces dramatically system complexity;the decoder has a source of power sink unit which rises in Add Compare-Select (ACS) unit. Various levels of development exist in VLSI such as architecture, microarchitecture, circuit, and transistor. ACS is structured of adder, comparator, and selector, so microarchitecture development of ACS unit intends one of these superior blocks. Adders in VLSI designs have a tremendous interest as they are the kernel of any digital system so enhancing this basic building block, which is used over and over, influences system specification. this paper targets different microarchitectural approaches to shrink the power of this unit which enhances overall system specification. Microarchitecture development encompasses using another block instead of the existing one or repositioning current blocks. In this review paper, comparisons of different parallel adders are presented to achieve low consumption power while obtaining high-speed operation of the addition, and an arrangement of ACS blocks to reduce the complexity of the decoder is also provided.

关键词： Radix-2 Fast Radix-2 parallel adders Carry Look-Ahead (CLA) Knowles Brent Kung (BK) and Sparse Kogge Stone (Sparse KS)

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Proceedings of the 13th international Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2023

Proceedings of the 13th International Symposium on Highly Ef...

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13th international Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2023

ISBN: (纸本)9798400700439

the proceedings contain 15 papers. the topics discussed include: extensible embedded hardware description languages with compilation, simulation and verification;breaking boundaries: optimizing FPGA CAD with flexible and multi-threaded re-clustering;efficient FPGA implementation of amoeba-inspired SAT solver with feedback and bounceback control: harnessing variable-level parallelism for large-scale problem solving in edge computing;quantitative study of floating-point precision on modern FPGAs;resource-efficient RISC-V vector extension architecture for FPGA-based accelerators;CSA based Radix-4 Gemmini systolic array for machine learning applications;and noise resilience of reduced precision neural networks.

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Efficient Differentially Private Tensor Factorization in the parallel and Distributed Computing Paradigm 21

Efficient Differentially Private Tensor Factorization in the...

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21st IEEE international Symposium on parallel and Distributed Processing with Applications, 13th IEEE international conference on Big Data and Cloud Computing, 16th IEEE international conference on Social Computing and Networking and 13th international conference on Sustainable Computing and Communications, ISPA/BDCloud/SocialCom/SustainCom 2023

作者： Zhang, Feng Wang, Hao Guo, Ruixin Xue, Erkang Qu, Guangzhi China University of Geosciences School of Computer Science Wuhan China Oakland University Department of Computer Science and Engineering Rochester United States

ISBN: (纸本)9798350329223

Tensor factorization plays a fundamental role in multiple areas of AI research. Nevertheless, it encounters significant challenges related to privacy breaches and operational efficiency. In this study, we propose a novel approach that addresses both of these issues simultaneously by integrating differential privacy with parallel and distributed computing. To accommodate diverse scenarios, we introduce two models: DPTF-SVRG and ADMM-DPTF, each leveraging specific techniques. DPTF-SVRG is designed for single-GPU environments and utilizes a unique strategy to reduce gradient variance, enabling faster convergence compared to SGD. Moreover, it achieves parallelism on the GPU through a lock-free asynchronous approach. On the other hand, ADMM-DPTF utilizes distributed ADMM to parallelize DPTF-SVRG, enabling multi-GPU parallelism. Experimental results demonstrate that our algorithms outperform existing benchmarks while maintaining differential privacy. © 2023 IEEE.

关键词： Tensors

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parallel and Batch Multiple Replica Auditing Protocol for Edge Computing 21

Parallel and Batch Multiple Replica Auditing Protocol for Ed...

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作者： Li, Yi Zheng, Wenying Pandi, Vijayakumar Bhuiyan, Md Zakirul Alam thamilarasi, C. Nanjing University of Information Science and Technology School of Computer Science Nanjing China Zhejiang Sci-Tech University School of Computer Science and Technology Hangzhou China University College of Engineering Tindivanam Anna University Chennai Department of Computer Science and Engineering Melpakkam India Fordham University Department of Computer and Information Sciences BronxNY United States P.S.V College of Enfgineering and Technoogy Department of Electronics and Communication Engineering Krishnagiri India

ISBN: (纸本)9798350329223

the edge computing architecture exposes data transmission and storage to unauthorized access, compromising data integrity. Users typically employ multiple data backups to ensure data reliability and availability, enhancing data redundancy and recovery capabilities. Nevertheless, verifying the integrity of multiple backup data under edge computing entails computational and communication overhead. In response, we present a parallel and batch multiple replica auditing protocol tailored for edge computing. Contributions include an efficient multiple replica construction method based on RSA, minimizing computational overhead, and a parallel data integrity verification approach that reduces communication overhead. A prototype implementation is evaluated in a real edge computing environment and compared to existing multiple replica auditing approaches. © 2023 IEEE.

关键词： Edge computing

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parallel Implementation of SHA256 on Multizone Heterogeneous Systems 21

Parallel Implementation of SHA256 on Multizone Heterogeneous...

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作者： Luo, Yongtao Liu, Jie Xiao, Tiaojie Gong, Chunye National University of Defense Technology Science and Technology on Parallel and Distributed Processing Laboratory Laboratory of Digitizing Program for Frontier Equipment Changsha China National Supercomputer Center in Tianjin Tianjin China

ISBN: (纸本)9798350329223

SHA-256 plays an important role in widely used applications, such as data security, data integrity, digital signatures, and cryptocurrencies. However, most of the current optimized implementations of SHA-256 are based on CPUs or dedicated hardware, such as ASICs and FPGAs. Consequently, there is a need to explore whether new heterogeneous parallel framework can improve the computational performance of the hash function. To address this issue, we conducted a study on the MT-3000 platform, which is a special architecture processor for the next-generation exascale prototype supercomputer. We proposed MT-SHA256, a heterogeneous multistage parallel implementation for hashing multiple messages on the MT-3000. Combining the architectural features of this processor, we developed an effective solution that significantly improved the computational performance of SHA-256. As a result, MT-SHA256 achieved a maximum throughput of 1045.68 MB/s on a single acceleration core of MT-3000. this is 9.84x higher than the C code implementation on one CPU core of MT-3000. We also performed a scalability test and found that MT-SHA256 achieved a throughput of 98.04 GB/s on a computing node, and extended to 512 nodes (2048 acceleration clusters) on this system with good scalability. © 2023 IEEE.

关键词： Hash functions

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13th international conference on Applications and techniques in Information Security, ATIS 2022

13th International Conference on Applications and Techniques...

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13th international conference on Applications and techniques in Information Security, ATIS 2022

ISBN: (纸本)9789819922635

the proceedings contain 23 papers. the special focus in this conference is on Applications and techniques in Information Security. the topics include: Enhancing Face Recognition Accuracy Using the ED-FFP Extraction Method and Ensemble Learning for Forensics and Cyber Security;intrusion Detection Using Federated Learning;analysis of Classification Algorithms for Predicting Parkinson’s Disease and Applications in the Field of Cybersecurity;Optimization of Secured Cluster Based Charging Dynamics and Scheduling of EV Using Deep RNN;analysis and Prognosis of Water Quality for River Ganga Using Water Quality Index;detection of Android Ransomware Using Machine Learning Approach;cyber Security and Layering of Medical Data Using Machine Learning Algorithms;analysis on Classification of Handwritten Devanagari Characters Using Deep Learning Models;analysis and Comparison of Different Frontend Frameworks;non-malleable Codes from Authenticated Encryption in Split-State Model;lightweight Capability-Based Access Control for Internet of things (IoT);securing IoT Using Blockchain;VIKAS: A Multimodal Framework to Aid in Effective Disaster Management;discovery of Rare Itemsets Using Hyper-Linked Data Structure: A parallel Approach;continuously Non-malleable Codes from Authenticated Encryptions in 2-Split-State Model;Deep Learning Based Differential Classifier of PRIDE and RC5;A Better MixColumns Matrix to AES Against Differential Fault Analysis Attack;variants of Crypto-Jacking Attacks and their Detection techniques;comparative Study of Sentiment Analysis on Cyber Security Related Multi-sourced Data in Social Media Platforms;modified Blowfish Encryption Algorithm for Wireless Body Area Network;eyeEncrypt: A Cyber-Secured Framework for Retinal Image Segmentation.

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