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检索条件"任意字段=14th ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA 2006"

共 40 条记录，以下是21-30 订阅

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Minimizing fpga reconfiguration data at logic level 06

Minimizing FPGA reconfiguration data at logic level

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7th international symposium on Quality Electronic Design

作者： Raghuraman, Krishna Wang, Haibo Tragoudas, Spyros So Illinois Univ Carbondale IL 62901 USA

ISBN: (纸本)0769525237

A framework that relates the size of fpga reconfiguration data to the number of minterms of a specially constructed function is presented. three techniques, variable mapping optimization, circuit don't-care modification, and look-up table input permutation, are developed to minimize minterms of the special function. the method to integrate the proposed techniques into fpga design automation flow is discussed and experimental results are presented.

关键词： field programmable gate arrays Reconfigurable logic Table lookup Hardware Circuits Design automation Partitioning algorithms Routing Cost function Scheduling

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Analysis and experimental results of an fpga-based strategy for fast production test of high resolution ADCs 06

Analysis and experimental results of an FPGA-based strategy ...

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7th international symposium on Quality Electronic Design

作者： De Venuto, Daniela Reyneri, Leonardo Politecn Bari Bari Italy Politecn Torino Turin Italy

ISBN: (纸本)0769525237

this work describes an intensive investigation on the test strategy known as polynomial fitting that uses fpga generated stimuli for cheap and fast testing of high resolution ADCs. Simulation and experimental results showed a sensitivity on the specifications parameters detection of 90dB. the proposed method can also help to control the cost of ADC production test, extends the test coverage and enable built-in self-test and test-based self-calibration.

关键词： Production Circuit testing Automatic testing Polynomials Built-in self-test Signal generators Linearity Histograms Performance evaluation field programmable gate arrays

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fpga Power Reduction by Guarded Evaluation 10

FPGA Power Reduction by Guarded Evaluation

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18th acm international symposium on field-programmable gate arrays

作者： Anderson, Jason H. Ravishankar, Chirag Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 1A1 Canada

ISBN: (纸本)9781605589114

Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times during circuit operation, thereby reducing switching activity and lowering dynamic power. the concept is rooted in the property that under certain conditions, some signals within digital designs are not "observable" at design outputs, making the circuitry that generates such signals a candidate for guarding. Guarded evaluation has been demonstrated successfully for custom ASICs;in this paper, we apply the technique to fpgas. In ASICs, guarded evaluation entails adding additional hardware to the design, increasing silicon area and cost. Here, we apply the technique in a way that imposes minimal area overhead by leveraging existing unused circuitry within the fpga. the primary challenge in guarded evaluation is in determining the specific conditions under which a sub-circuit's inputs can be held constant without impacting the larger circuit's functional correctness. We propose a simple solution to this problem based on discovering "non-inverting paths" in the circuit's AND-inverter graph representation. Experimental results show that guarded evaluation can reduce switching activity by 22%, on average, and can reduce power consumption in the fpga interconnect by 14%.

关键词： field-programmable gate arrays fpgas power optimization low-power design logic synthesis technology mapping

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Dual-Vt design of fpgas for subthreshold leakage tolerance 06

Dual-Vt design of FPGAs for subthreshold leakage tolerance

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7th international symposium on Quality Electronic Design

作者： Kumar, Akhilesh Anis, Mohab Univ Waterloo Dept ECE 200 Univ Ave W Waterloo ON N2L 3G1 Canada

ISBN: (纸本)0769525237

In this paper we propose a dual-Vt fpga architecture for reduction of subthreshold leakage power A CAD flow has been proposed based on the dual-Vt assignment algorithm and placement for realizing the dual-Vt fpga architecture. Logic elements within the logic blocks are the candidates for dual-Vt assignment. We propose an architecture in which there are two kinds of logic blocks, one with all high-Vt logic elements and another with a fixed percentage of high-Vt logic elements. these two kinds of logic blocks are then placed in such a way that the fpga architecture remains regular Results indicate that in the ideal case of dual-Vt assignment, over 95% of the logic elements can be assigned high-Vt. Results show that leakage savings of 55% can be achieved. Design tradeoffs for various ratios of the two kinds of logic blocks are investigated. the dual-Vt fpga CAD flow is intended for development and evaluation of dual-Vt fpga architectures.

关键词： field programmable gate arrays Subthreshold current Routing Switches Design automation Circuits threshold voltage Logic design Sleep MOS devices

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Global Delay Optimization using Structural Choices 10

Global Delay Optimization using Structural Choices

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18th acm international symposium on field-programmable gate arrays

作者： Mishchenko, Alan Brayton, Robert Jang, Stephen Univ Calif Berkeley Dept EECS Berkeley CA 94720 USA

ISBN: (纸本)9781605589114

this paper presents a fast global method for delay optimization after technology mapping. Timing analysis is used to identify timing-critical areas in the mapped network where new structures are synthesized to favor late-arriving signals. Unlike previous methods that make incremental local changes to the mapped network, the proposed method records many alternative structures and defers the final decision to the technology mapper. Experimental results for networks mapped into 6-input look-up tables (6-LUTs) show that the delay is, on average, improved 14% using a realistic delay library for LUTs with variable-pin delays and wire-delay estimation. the area penalty after the delay optimization is about 2% and can be eliminated by area-oriented resynthesis. When the algorithm is compared with DAOmap, the experimental results show 27% logic level reduction while the area is increased by only 1%. the algorithm is also fast and applicable to very large networks. the runtime of the proposed algorithm is 16x and 3x faster than DAOmap for large industrial and academic designs, respectively.

关键词： fpga Technology Mapping Logic Optimization Windowing Boolean Satisfiability Interpolation

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An Enhanced DSP Block Architecture for fpga Supporting Multi-operands Addition Operation 14

An Enhanced DSP Block Architecture for FPGA Supporting Multi...

引用

14th IEEE international Conference on ASIC, ASICON 2021

作者： Chen, Sanlin Cai, Gang Huang, Zhihong Chinese Academy of Sciences Aerospace Information Research Institute Beijing100094 China

ISBN: (纸本)9781665411493

the DSP block can effectively improve the performance of arithmetic operation in fpga. However, the commercial fpga does not directly support multi-operands addition operation which is used in multiple application scenarios such as FIR. Using traditional DSP block to realize multi-operands addition operation will take up a lot of logic resources and affect the performance. In this paper, three Multiplier or Addition Blocks (MABs) are proposed, which enable the DSP block to directly support multi-operands addition operation with high performance. Besides, an index to measure the area utilization rate of DSP block performing addition operation is proposed. Compared with the traditional method, the design proposed in this research can realize multi-operands addition operation by only using DSP block without occupying other logical resources in fpga. Based on Stratix-IV DSP block architecture, this experiment replaces multiplier with the MABs proposed in this paper. We use SMIC 40nm standard CMOS process to design and complete the implementation of the overall circuit. the experimental results show that the proposed design can realize two sets of eight 18-bit signed number addition operation at the cost of additional 7.48% area without affecting the existing functions of DSP block and the performance can reach 500MHz. © 2021 IEEE.

关键词： field programmable gate arrays (fpga)

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fpga clock network architecture: flexibility vs. area and power 06

FPGA clock network architecture: flexibility vs. area and po...

引用

Proceedings of the 2006 acm/sigda 14th international symposium on field programmable gate arrays

作者： Julien Lamoureux Steven J. E. Wilton University of British Columbia Vancouver B.C. Canada

ISBN: (纸本)9781595932921

this paper examines the tradeoffs between flexibility, area, and power dissipation of programmable clock networks for field-programmable gate arrays (fpga's). the paper begins by describing a parameterized clock network model that describes a broad range of programmable clock network architectures. Specifically, the model supports architectures with multiple local and global clock domains and varying amounts of flexibility at various levels of the clock network. Using the model, the architectural parameters that control the flexibility of the clock network are varied to determine the cost of this flexibility in terms of area and power dissipation. From these experiments, the study finds that area and power costs are highest for networks with flexibility close to the logic blocks. Furthermore, it found that clock networks with local clock domains have little overhead and are significantly more efficient than clock networks without local clock domains for applications with multiple clocks.

关键词： architecture clock network low-power fpga

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Periodic licensing of fpga based intellectual property 06

Periodic licensing of FPGA based intellectual property

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Proceedings of the 2006 acm/sigda 14th international symposium on field programmable gate arrays

作者： Nathaniel Couture Kenneth B. Kent University of New Brunswick Fredericton New Brunswick Canada

ISBN: (纸本)9781595932921

As field programmable gate arrays (fpga) gain popularity and become more prevalent in consumer products, the desire to have expiring fpga Intellectual Property(IP) will also rise. Up to this point, the sale of Intellectual Property (IP) targeting fpga-based consumer products have not been tremendously profitable for the creators of this IP. the sale of the products containing this IP however have been. this is due in part to the way the IP is licensed. this research investigates the feasibility of physically enforced periodic licensing of fpga IP. the goal is to design a hardware architecture to support licensable fpga IP cores targeting consumer products. this work describes a method of licensing IP on fpgas based on techniques derived from software licensing schemes. Current software and hardware licensing techniques are described in detail, including a survey of current research in the fields of fpga security, secure memory technologies, and cryptography. A licensing architecture for fpga IP is proposed, and an implementation on a Xilinx Virtex 2 fpga demonstrates that expiration of fpga based IP can be achieved. Future work includes the development of a hardware architecture for consumer products that supports licensable IP cores as well as their delivery.

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fpga based RAID 6 hardware accelerator 06

FPGA based RAID 6 hardware accelerator

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Proceedings of the 2006 acm/sigda 14th international symposium on field programmable gate arrays

作者： Michael Gilroy James Irvine William Berrie ISLI / A2ELtd Livingston Scotland Strathclyde University Glasgow Scotland A2E Ltd Livingston Scotland

ISBN: (纸本)9781595932921

Hard disk storage capacity has continued to rise whilst at the same time the cost per megabyte continues to fall. this, combined with increased usage of digital storage for documents, photography and video for both home and business use has led to increased need for reliable data storage system. Redundant arrays of inexpensive disks (RAID) have proven to offer the best characteristics for reliable storage. However, to date RAID based systems have been limited by their support for only single disk erasure *** paper introduces an efficient hardware RAID 6 controller on an fpga capable offering support for uninterrupted access during double disk erasures and recovery.

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Armada: timing-driven pipeline-aware routing for fpgas 06

Armada: timing-driven pipeline-aware routing for FPGAs

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Proceedings of the 2006 acm/sigda 14th international symposium on field programmable gate arrays

作者： Ken Eguro Scott Hauck University of Washington Seattle WA

ISBN: (纸本)9781595932921

While previous research has shown that fpgas can efficiently implement many types of computations, their flexibility inherently limits their clock rate. Several research groups have attempted to address this by developing new architectures that include registered switchpoints within their interconnect. Unfortunately, this pipelined communication presents a new and difficult problem for detailed routing tools. Known as the N-Delay Routing Problem, it has been proven to be NP-Complete. Although there have been two heuristics developed to address this issue, both have certain limitations and neither approach considers timing during the routing process. While timing-driven conventional routing is largely considered to be a solved problem, there are several issues inherent to the N-Delay Routing problem make addressing timing particularly difficult. In this paper we discuss the nature of these problems and present a new timing-driven pipeline-aware router that produces as much as 60% better critical path delay than previous efforts.

关键词： pipeline fpga pipeline routing reconfigurable computing

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