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检索条件"任意字段=14th ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA 2006"

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Periodic licensing of fpga based intellectual property 06

Periodic licensing of FPGA based intellectual property

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Proceedings of the 2006 acm/sigda 14th international symposium on field programmable gate arrays

作者： Nathaniel Couture Kenneth B. Kent University of New Brunswick Fredericton New Brunswick Canada

ISBN: (纸本)9781595932921

As field programmable gate arrays (fpga) gain popularity and become more prevalent in consumer products, the desire to have expiring fpga Intellectual Property(IP) will also rise. Up to this point, the sale of Intellectual Property (IP) targeting fpga-based consumer products have not been tremendously profitable for the creators of this IP. the sale of the products containing this IP however have been. this is due in part to the way the IP is licensed. this research investigates the feasibility of physically enforced periodic licensing of fpga IP. the goal is to design a hardware architecture to support licensable fpga IP cores targeting consumer products. this work describes a method of licensing IP on fpgas based on techniques derived from software licensing schemes. Current software and hardware licensing techniques are described in detail, including a survey of current research in the fields of fpga security, secure memory technologies, and cryptography. A licensing architecture for fpga IP is proposed, and an implementation on a Xilinx Virtex 2 fpga demonstrates that expiration of fpga based IP can be achieved. Future work includes the development of a hardware architecture for consumer products that supports licensable IP cores as well as their delivery.

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fpga based RAID 6 hardware accelerator 06

FPGA based RAID 6 hardware accelerator

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Proceedings of the 2006 acm/sigda 14th international symposium on field programmable gate arrays

作者： Michael Gilroy James Irvine William Berrie ISLI / A2ELtd Livingston Scotland Strathclyde University Glasgow Scotland A2E Ltd Livingston Scotland

ISBN: (纸本)9781595932921

Hard disk storage capacity has continued to rise whilst at the same time the cost per megabyte continues to fall. this, combined with increased usage of digital storage for documents, photography and video for both home and business use has led to increased need for reliable data storage system. Redundant arrays of inexpensive disks (RAID) have proven to offer the best characteristics for reliable storage. However, to date RAID based systems have been limited by their support for only single disk erasure *** paper introduces an efficient hardware RAID 6 controller on an fpga capable offering support for uninterrupted access during double disk erasures and recovery.

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Evaluation of granularity on threshold voltage control in flex power fpga 06

Evaluation of granularity on threshold voltage control in fl...

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Proceedings of the 2006 acm/sigda 14th international symposium on field programmable gate arrays

作者： Masakazu Hioki Takashi Kawanami Toshiyuki Tsutsumi Tadashi Nakagawa Toshihiro Sekigawa Hanpei Koike National Institute of Advanced Industrial Science and Technology (AIST) Ibaraki-ken Japan Meiji University Kanagawa-ken Japan National Institute of Advanced Industrial Science and Technology (AIST) Ibaraki-ken Japan

ISBN: (纸本)9781595932921

Flex Power fpga can flexibly control the operating speed and power consumption by flexible assignment of the threshold voltage to transistor. this paper evaluates the static power consumption and area overhead on various threshold voltage control granularity in the Flex Power fpga based on specific settings. there is the trade-off relationship between static power and area overhead in threshold voltage control granularity in Flex Power fpga with bulk MOS transistors. Moreover, division of the threshold voltage controlled transistor area has a big influence on the trade-off. For example of evaluation results, static power reduces less than 1/5 of original level, while increase an area overhead of less than 40% by appropriately dividing the threshold voltage controlled transistor areas. If an area increase of 50% is allowed, then the reduction in static power consumption to 1/10 or less is obtained.

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Armada: timing-driven pipeline-aware routing for fpgas 06

Armada: timing-driven pipeline-aware routing for FPGAs

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Proceedings of the 2006 acm/sigda 14th international symposium on field programmable gate arrays

作者： Ken Eguro Scott Hauck University of Washington Seattle WA

ISBN: (纸本)9781595932921

While previous research has shown that fpgas can efficiently implement many types of computations, their flexibility inherently limits their clock rate. Several research groups have attempted to address this by developing new architectures that include registered switchpoints within their interconnect. Unfortunately, this pipelined communication presents a new and difficult problem for detailed routing tools. Known as the N-Delay Routing Problem, it has been proven to be NP-Complete. Although there have been two heuristics developed to address this issue, both have certain limitations and neither approach considers timing during the routing process. While timing-driven conventional routing is largely considered to be a solved problem, there are several issues inherent to the N-Delay Routing problem make addressing timing particularly difficult. In this paper we discuss the nature of these problems and present a new timing-driven pipeline-aware router that produces as much as 60% better critical path delay than previous efforts.

关键词： pipeline fpga pipeline routing reconfigurable computing

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Efficient use of communications between an fpga's embedded processor and its reconfigurable logic 06

Efficient use of communications between an FPGA's embedded p...

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Proceedings of the 2006 acm/sigda 14th international symposium on field programmable gate arrays

作者： Joshua Noseworthy Miriam Leeser Mercury Computer Systems Chelmsford MA Northeastern University Boston MA

ISBN: (纸本)9781595932921

fpga manufacturers have recently embedded hard core microprocessors in fpga fabric to improve the processing capabilities of their architectures. We present a study of using the Xilinx Virtex family's embedded PowerPC405 processor. We use a Software Defined Radio (SDR) application as a vehicle for investigating effective communications between the PowerPC405 Processor and the surrounding fpga fabric. A challenging aspect of developing applications that target the PowerPC is the interfacing of the processor with the surrounding reconfigurable logic. We have implemented a dozen different versions of a Software Defined Radio (SDR) application to exercise the various interfaces that enable communication between the processor and the surrounding fpga fabric. the implementations differ only in the interfaces used. Our study investigates the use of the On Chip Memory (OCM) interface, the Processor Local Bus (PLB) and the On-chip Processor Bus (OPB).We investigate the best interfaces for different data including instructions, stack, heap and user data. Our results indicate that the performance of the SDR application can be increased by as much as 60 percent just by choosing the interfaces that are most appropriate for the different types of data in the implementation. this demonstrates that the performance of fpga applications that use the embedded processor are dramatically effected by the mechanisms chosen to enable communication between the processor and its surrounding resources.

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A novel methodology for designing high-performance and low-energy fpga routing architecture 06

A novel methodology for designing high-performance and low-e...

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Proceedings of the 2006 acm/sigda 14th international symposium on field programmable gate arrays

作者： Konstantinos Siozios Konstantinos Tatas Dimitrios Soudris Antonios thanailakis Democritus University of Thrace Xanthi Greece

ISBN: (纸本)9781595932921

fpga architecture characteristics and capabilities changed and improved significantly the last years, from a homogeneous and regular architecture to a heterogeneous (or piece-wise homogeneous) and piece-wise regular architecture. the platform-based design allows to designer to build a customized fpga architecture, using specific blocks, depending on the application domain requirements. Due to the fact that about 70-90% of typical an fpga is occupied by routing resources, many researchers have spent much effort on minimizing energy consumption and on achieving higher frequencies. their clear message was the fact that the interconnection structure dominates the total power dissipation and performance. A typical interconnection network of fpga consists of the Switch Boxes (SBs) and the wire segments. In this paper, we propose a novel methodology for designing a high-performance and low-energy routing architecture of an island style-based fpga platform. the basic idea behind the new methodology is to choose the corresponding performance and energy efficient combination of multiple SBs and the appropriate wire segment, taking into account the considered application-domain characteristics. More specifically, the proposed methodology selects the appropriate combination of SBs, depending on the localized performance and energy consumption requirements of each specific region of fpga architecture. the efficiency of an SB and wire segment is characterized by analyzing parameters such as performance, energy dissipation and the number of required tracks for successful application routing. Using MCNC benchmarks, extensive comparison study proves the effectiveness of the proposed approach achieving performance increase of 52% and reduction of energy consumption 12%, in average.

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A multilevel hierarchical interconnection structure for fpga 06

A multilevel hierarchical interconnection structure for FPGA

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Proceedings of the 2006 acm/sigda 14th international symposium on field programmable gate arrays

作者： Hayder Mrabet Zied Marrakchi Pierre Souillot Habib Mehrez Université Pierre et Marie Curie Paris France Ecole Polytechnique France

ISBN: (纸本)9781595932921

Creation of large fpgas needs radical efficient changes in architecture to improve speed, density and software mapping time. Based on industry experience with standard ASICs, we believe that partitioning and hierarchy become an obligation for fpga hardware and software developments. As an alternative we propose a new Multilevel hierarchical fpga (Mfpga) architecture where logic blocks and routing resources are sparsely partitioned into multilevel clustered structure. Since the routing resources consume most of the fpga area, we focus on interconnect check. We try to achieve the best area efficiency by balancing interconnect and logic block utilization. the proposed Mfpga interconnect unifies two unidirectional programmable networks: A downward network based on the Butterfly-Fat-Tree topology, and an upward network that uses hierarchy. the Downward network uses linear populated and unidirectional switch boxes and gives one path from each wire-source in the top to each leaf (logic block) in the lowest level. the upward network connects the logic blocks outputs and the input pads to the different levels of the downward network. Studies based on the Rent's Rule show that wiring and switch requirements in the Mfpga grow slower than in traditional topologies. We used MCNC benchmark circuits to compare the switch and area requirements between our Mfpga architecture and the traditional mesh topology. New software tools for placement and routing were developed to conduct this study on the Mfpga architecture. Expermimental results show that Mfpga can implement circuits with fewer switches and a smaller total area than mesh architecture.

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A programmable majority logic array using molecular scale electronics 06

A programmable majority logic array using molecular scale el...

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Proceedings of the 2006 acm/sigda 14th international symposium on field programmable gate arrays

作者： Garrett S. Rose Mircea R. Stan University of Virginia Charlottesville VA

ISBN: (纸本)9781595932921

We present a computer architecture design that utilizes molecular electronic devices fabricated from self-assembled monolayers (SAM) of molecules. this architecture has been designed for a process being developed at the University of Virginia where molecules are assembled via vapor phase deposition. As this process lends itself nicely to developing multiple layers of devices on a single substrate, the circuit and architectural designs presented here exist in three dimensions. through this work we show how molecular electronics naturally allows for 3D integration at the *** design consists of two types of molecular devices: switches with memory and resonant tunneling diodes (RTD). these switching molecules are patterned between layers of metal to form a uniform crossbar array that can behave similar to a programmable logic array (PLA). In this design, the crossbar arrays drive rows of circuits, referred to as Goto pairs, consisting of two stacked molecular RTDs. As described in previous work, a Goto pair with only one resistor driving its input functions as a latch whereas the circuit acts as a majority gate when driven by multiple resistors. Since the crossbar arrays can be programmed such that the various Goto pairs are driven by different numbers of inputs, the overall circuit has the ability to implement logic as networks of latches and majority gates. Using crossbar arrays in this way is somewhat different from other approaches in that logic is not simply implemented in the array but is a product of both the array and the Goto pair functionality.

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Configuration tools for a new multilevel hierarchical fpga 06

Configuration tools for a new multilevel hierarchical FPGA

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Proceedings of the 2006 acm/sigda 14th international symposium on field programmable gate arrays

作者： Marrakchi Zied Mrabet Hayder Mehrez Habib LIP6 12 rue cuvier Paris

ISBN: (纸本)9781595932921

In this paper we evaluate a new multi-level hierarchical Mfpga. the specific architecture includes two unidirectional programmable networks: A downward network based on the Butterfly-Fat-Tree topology and a special hierarchical upward network. the Downward network uses linear populated and unidirectional Switch Boxes (SBs) and gives one path from each wire-source in the top to reach a leaf (Logic Block: LB) in the lowest level. the upward network connects the LBs output and the input Pads to the SBs situated in different levels of the downward network. New tools are developed to program the new architecture. the global placement approach uses a combination of clustering and partitioning with adaptations to deal with the multi-level interconnect topology. First we run a multi-level bottom-up clustering to reduce external connections. Second we run a multi-level top-down refinement to reduce signals bandwidth of clusters in each level. A detailed placer defines the position of each LB inside a cluster and considers more complex routing constraints. the router is an adaptation of Pathfinder. the global routing consists on selecting the level to use. Signals routing is immediate since path to reach a destination is predictable and unique. Results are based on the MCNC benchmarks and they quantify the LB occupancy and routability. Comparison with the traditional symmetric Manhattan mesh architecture shows that Mfpga can implement circuits with fewer switches and a smaller total area.

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Placement-driven technology mapping for LUT-based fpgas

Placement-driven technology mapping for LUT-based FPGAs

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acm/sigda 11th acm international symposium on field programmable gate arrays

作者： Lin, Joey Y. Jagannathan, Ashok Cong, Jason

In this paper, we study the problem of placement-driven technology mapping for table-lookup based fpga architectures to optimize circuit performance. Early work on technology mapping for fpgas such as Chortle-d[14] and Flowmap[3] aim to optimize the depth of the mapped solution without consideration of interconnect delay. Later works such as Flowmap-d[7], Bias-Clus[4] and EdgeMap consider interconnect delays during mapping, but do not take into consideration the effects of their mapping solution on the final placement. Our work focuses on the interaction between the mapping and placement stages. First, the interconnect delay information is estimated from the placement, and used during the labeling process. A placement-based mapping solution which considers both global cell congestion and local cell congestion is then developed. Finally, a legalization step and detailed placement is performed to realize the design. We have implemented our algorithm in a LUT based fpga technology mapping package named PDM (Placement-Driven Mapping) and tested the implementation on a set of MCNC benchmarks. We use the tool VPR[1][2] for placement and routing of the mapped netlist. Experimental results show the longest path delay on a set of large MCNC benchmarks decreased by 12.3% on the average.

关键词： field programmable gate arrays

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