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Evaluation of granularity on threshold voltage control in flex power fpga 06

Evaluation of granularity on threshold voltage control in fl...

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Proceedings of the 2006 acm/sigda 14th international symposium on field programmable gate arrays

作者： Masakazu Hioki Takashi Kawanami Toshiyuki Tsutsumi Tadashi Nakagawa Toshihiro Sekigawa Hanpei Koike National Institute of Advanced Industrial Science and Technology (AIST) Ibaraki-ken Japan Meiji University Kanagawa-ken Japan National Institute of Advanced Industrial Science and Technology (AIST) Ibaraki-ken Japan

ISBN: (纸本)9781595932921

Flex Power fpga can flexibly control the operating speed and power consumption by flexible assignment of the threshold voltage to transistor. this paper evaluates the static power consumption and area overhead on various threshold voltage control granularity in the Flex Power fpga based on specific settings. there is the trade-off relationship between static power and area overhead in threshold voltage control granularity in Flex Power fpga with bulk MOS transistors. Moreover, division of the threshold voltage controlled transistor area has a big influence on the trade-off. For example of evaluation results, static power reduces less than 1/5 of original level, while increase an area overhead of less than 40% by appropriately dividing the threshold voltage controlled transistor areas. If an area increase of 50% is allowed, then the reduction in static power consumption to 1/10 or less is obtained.

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Efficient use of communications between an fpga's embedded processor and its reconfigurable logic 06

Efficient use of communications between an FPGA's embedded p...

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Proceedings of the 2006 acm/sigda 14th international symposium on field programmable gate arrays

作者： Joshua Noseworthy Miriam Leeser Mercury Computer Systems Chelmsford MA Northeastern University Boston MA

ISBN: (纸本)9781595932921

fpga manufacturers have recently embedded hard core microprocessors in fpga fabric to improve the processing capabilities of their architectures. We present a study of using the Xilinx Virtex family's embedded PowerPC405 processor. We use a Software Defined Radio (SDR) application as a vehicle for investigating effective communications between the PowerPC405 Processor and the surrounding fpga fabric. A challenging aspect of developing applications that target the PowerPC is the interfacing of the processor with the surrounding reconfigurable logic. We have implemented a dozen different versions of a Software Defined Radio (SDR) application to exercise the various interfaces that enable communication between the processor and the surrounding fpga fabric. the implementations differ only in the interfaces used. Our study investigates the use of the On Chip Memory (OCM) interface, the Processor Local Bus (PLB) and the On-chip Processor Bus (OPB).We investigate the best interfaces for different data including instructions, stack, heap and user data. Our results indicate that the performance of the SDR application can be increased by as much as 60 percent just by choosing the interfaces that are most appropriate for the different types of data in the implementation. this demonstrates that the performance of fpga applications that use the embedded processor are dramatically effected by the mechanisms chosen to enable communication between the processor and its surrounding resources.

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A multilevel hierarchical interconnection structure for fpga 06

A multilevel hierarchical interconnection structure for FPGA

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Proceedings of the 2006 acm/sigda 14th international symposium on field programmable gate arrays

作者： Hayder Mrabet Zied Marrakchi Pierre Souillot Habib Mehrez Université Pierre et Marie Curie Paris France Ecole Polytechnique France

ISBN: (纸本)9781595932921

Creation of large fpgas needs radical efficient changes in architecture to improve speed, density and software mapping time. Based on industry experience with standard ASICs, we believe that partitioning and hierarchy become an obligation for fpga hardware and software developments. As an alternative we propose a new Multilevel hierarchical fpga (Mfpga) architecture where logic blocks and routing resources are sparsely partitioned into multilevel clustered structure. Since the routing resources consume most of the fpga area, we focus on interconnect check. We try to achieve the best area efficiency by balancing interconnect and logic block utilization. the proposed Mfpga interconnect unifies two unidirectional programmable networks: A downward network based on the Butterfly-Fat-Tree topology, and an upward network that uses hierarchy. the Downward network uses linear populated and unidirectional switch boxes and gives one path from each wire-source in the top to each leaf (logic block) in the lowest level. the upward network connects the logic blocks outputs and the input pads to the different levels of the downward network. Studies based on the Rent's Rule show that wiring and switch requirements in the Mfpga grow slower than in traditional topologies. We used MCNC benchmark circuits to compare the switch and area requirements between our Mfpga architecture and the traditional mesh topology. New software tools for placement and routing were developed to conduct this study on the Mfpga architecture. Expermimental results show that Mfpga can implement circuits with fewer switches and a smaller total area than mesh architecture.

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A novel methodology for designing high-performance and low-energy fpga routing architecture 06

A novel methodology for designing high-performance and low-e...

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Proceedings of the 2006 acm/sigda 14th international symposium on field programmable gate arrays

作者： Konstantinos Siozios Konstantinos Tatas Dimitrios Soudris Antonios thanailakis Democritus University of Thrace Xanthi Greece

ISBN: (纸本)9781595932921

fpga architecture characteristics and capabilities changed and improved significantly the last years, from a homogeneous and regular architecture to a heterogeneous (or piece-wise homogeneous) and piece-wise regular architecture. the platform-based design allows to designer to build a customized fpga architecture, using specific blocks, depending on the application domain requirements. Due to the fact that about 70-90% of typical an fpga is occupied by routing resources, many researchers have spent much effort on minimizing energy consumption and on achieving higher frequencies. their clear message was the fact that the interconnection structure dominates the total power dissipation and performance. A typical interconnection network of fpga consists of the Switch Boxes (SBs) and the wire segments. In this paper, we propose a novel methodology for designing a high-performance and low-energy routing architecture of an island style-based fpga platform. the basic idea behind the new methodology is to choose the corresponding performance and energy efficient combination of multiple SBs and the appropriate wire segment, taking into account the considered application-domain characteristics. More specifically, the proposed methodology selects the appropriate combination of SBs, depending on the localized performance and energy consumption requirements of each specific region of fpga architecture. the efficiency of an SB and wire segment is characterized by analyzing parameters such as performance, energy dissipation and the number of required tracks for successful application routing. Using MCNC benchmarks, extensive comparison study proves the effectiveness of the proposed approach achieving performance increase of 52% and reduction of energy consumption 12%, in average.

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A programmable majority logic array using molecular scale electronics 06

A programmable majority logic array using molecular scale el...

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Proceedings of the 2006 acm/sigda 14th international symposium on field programmable gate arrays

作者： Garrett S. Rose Mircea R. Stan University of Virginia Charlottesville VA

ISBN: (纸本)9781595932921

We present a computer architecture design that utilizes molecular electronic devices fabricated from self-assembled monolayers (SAM) of molecules. this architecture has been designed for a process being developed at the University of Virginia where molecules are assembled via vapor phase deposition. As this process lends itself nicely to developing multiple layers of devices on a single substrate, the circuit and architectural designs presented here exist in three dimensions. through this work we show how molecular electronics naturally allows for 3D integration at the *** design consists of two types of molecular devices: switches with memory and resonant tunneling diodes (RTD). these switching molecules are patterned between layers of metal to form a uniform crossbar array that can behave similar to a programmable logic array (PLA). In this design, the crossbar arrays drive rows of circuits, referred to as Goto pairs, consisting of two stacked molecular RTDs. As described in previous work, a Goto pair with only one resistor driving its input functions as a latch whereas the circuit acts as a majority gate when driven by multiple resistors. Since the crossbar arrays can be programmed such that the various Goto pairs are driven by different numbers of inputs, the overall circuit has the ability to implement logic as networks of latches and majority gates. Using crossbar arrays in this way is somewhat different from other approaches in that logic is not simply implemented in the array but is a product of both the array and the Goto pair functionality.

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Configuration tools for a new multilevel hierarchical fpga 06

Configuration tools for a new multilevel hierarchical FPGA

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Proceedings of the 2006 acm/sigda 14th international symposium on field programmable gate arrays

作者： Marrakchi Zied Mrabet Hayder Mehrez Habib LIP6 12 rue cuvier Paris

ISBN: (纸本)9781595932921

In this paper we evaluate a new multi-level hierarchical Mfpga. the specific architecture includes two unidirectional programmable networks: A downward network based on the Butterfly-Fat-Tree topology and a special hierarchical upward network. the Downward network uses linear populated and unidirectional Switch Boxes (SBs) and gives one path from each wire-source in the top to reach a leaf (Logic Block: LB) in the lowest level. the upward network connects the LBs output and the input Pads to the SBs situated in different levels of the downward network. New tools are developed to program the new architecture. the global placement approach uses a combination of clustering and partitioning with adaptations to deal with the multi-level interconnect topology. First we run a multi-level bottom-up clustering to reduce external connections. Second we run a multi-level top-down refinement to reduce signals bandwidth of clusters in each level. A detailed placer defines the position of each LB inside a cluster and considers more complex routing constraints. the router is an adaptation of Pathfinder. the global routing consists on selecting the level to use. Signals routing is immediate since path to reach a destination is predictable and unique. Results are based on the MCNC benchmarks and they quantify the LB occupancy and routability. Comparison with the traditional symmetric Manhattan mesh architecture shows that Mfpga can implement circuits with fewer switches and a smaller total area.

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A streaming fpga implementation of a steerable filter for real-time applications (abstract only) 11

A streaming FPGA implementation of a steerable filter for re...

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Proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Srinidhi Kestur Dharav Dantara Vijaykrishnan Narayanan The Pennsylvania State University University Park PA USA

ISBN: (纸本)9781450305549

Oriented filters are used in many early vision and image processing tasks for feature extraction at arbitrary orientations. Steerable filters are a class of filters in which a filter of arbitrary orientation is synthesized as a linear combination of a set of basis filters. In this work, we describe a streaming implementation of a steerable filter on fpgas, which includes a two-dimensional convolution filter and a modulator for modulation by a set of oriented sine waves. We present a highly configurable streaming 2D convolution implementation and a novel separable look-up-table based implementation of the modulation step. this steerable filter has been extended to multiple resolutions to realize a steerable pyramid filter. Experimental results on a Virtex6 fpga show that the steerable pyramid filter provides up to 14X and 21X speedups over related fpga and CPU implementations respectively. this work was supported in part by a grant from NSF 0916887 and DARPA Neovision2 programs.

关键词： pyramid filter ml605 gabor filter fpga implementation convolution steerable filter modulation

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Design space exploration of throughput-optimized arrays from recurrence abstractions (abstract only) 10

Design space exploration of throughput-optimized arrays from...

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Proceedings of the 18th annual acm/sigda international symposium on field programmable gate arrays

作者： Arpith C. Jacob Jeremy D. Buhler Roger D. Chamberlain Washington University in St. Louis St. Louis MO USA

ISBN: (纸本)9781605589114

Many compute-bound software applications have seen order-of-magnitude speedups using application-specific accelerators built on specialized architectures such as field-programmable gate arrays. these architectures are particularly good at implementing systems of recurrence equations realized as systolic arrays. We pursue high-level synthesis tools for recurrence equations that can search the space of possible parallel array designs to optimize various design criteria. Most existing approaches produce an array that is latency-space optimal. We target applications that operate on a large collection of small inputs, e.g. a database of biological sequences. For these applications, overall throughput, rather than latency per input, is the most important measure of *** this work we introduce a new design space exploration procedure to optimize throughput of a systolic array subject to area and bandwidth constraints of an fpga device. We show that the throughput of an array is dependent on the maximum number of lattice points executed by any processor in the array, which is determined solely by the array's projection vector. We describe a bounded search process to find throughput-optimized projection vectors, discovering a range of array designs that are optimal for inputs of various *** have written a tool in C++ that accepts recurrence descriptions and produces throughput-optimized array mappings. We have applied our technique to the banded Smith-Waterman and Nussinov RNA folding algorithms, and present novel arrays that are 4-33x and 2-14x faster, respectively, than the currently-used latency-optimized array.

关键词： dynamic programming systolic array throughput optimization fpga recurrences

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A Novel Development for Parallel Cyclic Convolution: the Super Block Pseudocirculant Matrix

A Novel Development for Parallel Cyclic Convolution: The Sup...

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Quality of Service, 2006 14th IEEE international Workshop on;Princeton,NJ

作者： Marvi Teixeira Y. Ivan Rodriguez Angel Gonzalez Electrical and Computer Engineering and Computer Science Department Polytechnic University of Puerto Rico Hato Rey Puerto Rico

As opposed to Prime Factor type algorithms, the only requirement made by parallel cyclic convolution techniques based on block Pseudocirculant matrices is that the convolution length be composite. Highly composite lengths, in particular, give a larger variety of implementation choices. In this paper we offer an introduction to new mathematical constructs, the Super Block Pseudocirculant Matrix, and the Block Pseudocyclic Shift Operator, as a base to derive further structures for this important class of parallel, one dimensional, cyclic convolution algorithms based on block pseudocirculant matrices. their modular composition makes them suitable for implementation in VLSI, fpga or multiprocessor computers in either a pipelined or a parallel fashion. Block pseudocirculants appear in fields such as precoding systems, transmultiplexers, polyphase networks, block filtering, QMF banks, and others, therefore the new mathematical constructs introduced in this paper may have an impact that transcend its sole applications to parallel cyclic convolution and its related applications.

关键词： Convolution Tin Concurrent computing Very large scale integration Computer science field programmable gate arrays Filter bank Filtering Application software Discrete cosine transforms

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An Architecture for Exploiting Multi-Core Processors to Parallelize Network Intrusion Prevention

An Architecture for Exploiting Multi-Core Processors to Para...

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Quality of Service, 2006 14th IEEE international Workshop on;Princeton,NJ

作者： Vern Paxson Robin Sommer Nicholas Weaver Lawrence Berkeley National Laboratory International Computer Science Institute International Computer Science Institute

It is becoming increasingly difficult to implement effective systems for preventing network attacks, due to the combination of (1) the rising sophistication of attacks requiring more complex analysis to detect, (2) the relentless growth in the volume of network traffic that we must analyze, and, critically, (3) the failure in recent years for uniprocessor performance to sustain the exponential gains that for so many years CPUs enjoyed ("Moore's Law"). For commodity hardware, tomorrow's performance gains will instead come from multicore architectures in which a whole set of CPUs executes concurrently. Taking advantage of the full power of multi-core processors for network intrusion prevention requires an in-depth approach. In this work we frame an architecture customized for parallel execution of network attack analysis. At the lowest layer of the architecture is an "Active Network Interface" (ANI), a custom device based on an inexpensive fpga platform. the ANI provides the inline interface to the network, reading in packets and forwarding them after they are approved. It also serves as the front-end for dispatching copies of the packets to a set of analysis threads. the analysis itself is structured as an event-based system, which allows us to find many opportunities for concurrent execution, since events introduce a natural, decoupled asynchrony into the flow of analysis while still maintaining good cache locality. Finally, by associating events with the packets that ultimately stimulated them, we can determine when all analysis for a given packet has completed, and thus that it is safe to forward the pending packet - providing none of the analysis elements previously signaled that the packet should instead be discarded.

关键词： Multicore processing Failure analysis Performance analysis Performance gain Signal analysis Telecommunication traffic Hardware field programmable gate arrays Dispatching Yarn

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