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检索条件"任意字段=14th ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems"

共 48 条记录，以下是11-20 订阅

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SmartVisor: User-Friendly Hypervisor for Mobile Robots 25

SmartVisor: User-Friendly Hypervisor for Mobile Robots

引用

25th acm sigplan/sigbed International conference on languages, compilers, and tools for embedded systems (LCTES)

作者： Chen, Guanyu Lv, Pan Li, Hong Yang, Guoqing Zhejiang Univ Hangzhou Peoples R China

ISBN: (纸本)9798400706165

With the increasing prevalence of mobile robots, there is a growing demand for powerful system software. Integrating multiple operating systems into a single platform has become necessary, and virtualization offers a cost-effective solution for managing multiple OSes. While several types of hypervisors for embedded systems have been proposed to manage guest OSes, significant work is still needed to make hypervisors applicable in robot systems. this paper introduces SmartVisor, a microkernel-based hypervisor designed explicitly for robotic systems. Our work focuses on designing the virtual machine management module to improve robot performance and user experience. the goal is to ensure that the hypervisor-based robot meets the demands of real-world scenarios for robot developers and users.

关键词： Virtualization embedded System Robot Operating System

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A JVM for Soft-Error-Prone embedded systems

A JVM for Soft-Error-Prone Embedded Systems

引用

14th acm sigplan/sigbed conference on languages, compilers and tools for embedded systems

作者： Stilkerich, Isabella Strotz, Michael Erhardt, Christoph Hoffmann, Martin Lohmann, Daniel Scheler, Fabian Schroeder-Preikschat, Wolfgang Univ Erlangen Nurnberg Nurnberg Germany

ISBN: (纸本)9781450320856

the reduction of structure sizes in microcontollers, environmental conditions or low supply voltages increase the susceptibility of embedded systems to soft errors. As a result, the employment of fault-detection and fault-tolerance measures is becoming a mandatory task even for moderately critical applications. Accordingly, software-based techniques have recently gained in popularity, and a multitude of approaches that differ in the number and frequency of tolerated errors as well as their associated overhead have been proposed. Using type-safe programming languages to isolate critical software components is very popular among those techniques. An automated application of fault-detection and fault-tolerance measures based on the type system of the programming language and static code analyses is possible. It facilitates an easy evaluation of the protection characteristics and costs as well as the migration of software to new hardware platforms with different failure rates. Transient faults, however, are not bound to the application code secured by the type system, but can also affect the correctness of the type system itself. thereby, the type system might lose its ability to isolate critical components. As a consequence, it is essential to also protect the type system itself against soft errors. In this paper, we show how soft errors can affect the integrity of the type system. Furthermore, we provide means to secure it against these faults, thus preserving its isolating character. these measures can be applied selectively to achieve a suitable tradeoff between level of protection and resource consumption. (1)

关键词： Reliability Design languages KESO Java RTSJ embedded systems Real-Time systems Reliability

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LUNAR: A Native Table Engine for embedded Devices 2023

LUNAR: A Native Table Engine for Embedded Devices

引用

24th acm sigplan/sigbed International conference on languages, compilers, and tools for embedded systems (LCTES)

作者： Fan, Xiaopeng Yan, Song Huang, Yuchen Weng, Chuliang East China Normal Univ Shanghai Peoples R China

ISBN: (纸本)9798400701740

embedded systems have evolved tremendously in recent years. We perform a study on SQLite and find that the multiple layers of abstraction drastically reduce bandwidth utilization. To minimize the bandwidth loss in the I/O path, we propose LUNAR, a novel native table storage engine. LUNAR performs a cross-layer design across the database and file system to avoid the pitfalls of multi-layer abstraction while providing SQL-compatible APIs. It employs a type-aware storage layout that considers the access patterns of different data types. then, LUNAR designs a variable-size allocator to reduce fragmentation and optimize RAM and I/O bandwidth usage. Further, considering the limited resources on embedded devices, LUNAR employs a modular architecture that enables selecting modules on demand. It also offers optional consistency modes to make a trade-off between resource consumption and consistency. Experiments show that LUNAR achieves higher bandwidth utilization, outperforming state-of-the-art approaches while consuming fewer resources.

关键词： embedded devices storage management modularity consistency

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MinUn: Accurate ML Inference on Microcontrollers 2023

MinUn: Accurate ML Inference on Microcontrollers

引用

24th acm sigplan/sigbed International conference on languages, compilers, and tools for embedded systems (LCTES)

作者： Jaiswal, Shikhar Goli, Rahul Kranti Kiran Kumar, Aayan Seshadri, Vivek Sharma, Rahul Microsoft Res Bengaluru India Univ Toronto Toronto ON Canada Swiss Fed Inst Technol Zurich Switzerland Linea Labs Inc San Francisco CA USA

ISBN: (纸本)9798400701740

Running machine learning inference on tiny devices, known as TinyML, is an emerging research area. this task requires generating inference code that uses memory frugally, a task that standard ML frameworks are ill-suited for. A deployment framework for TinyML must a) be parametric in the number representation to take advantage of the emerging representations like posits, b) carefully assign high-precision to a few tensors so that most tensors can be kept in low-precision while still maintaining model accuracy, and c) avoid memory fragmentation. We describe MinUn, the first TinyML framework that holistically addresses these issues to generate efficient code for ARM microcontrollers (e.g., Arduino Uno, Due and STM32H747) that outperforms the prior TinyML

关键词： TinyML Memory Management Programming languages compilers Number Representations embedded Devices

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Practical Speculative Parallelization of Variable-Length Decompression Algorithms

Practical Speculative Parallelization of Variable-Length Dec...

引用

14th acm sigplan/sigbed conference on languages, compilers and tools for embedded systems

作者： Jang, Hakbeom Kim, Channoh Lee, Jae W. Sungkyunkwan Univ Suwon 440746 South Korea

ISBN: (纸本)9781450320856

Variable-length coding is widely used for efficient data compression. Typically, the compressor splits the original data into blocks and compresses each block with variable-length codes, hence producing variable-length compressed blocks. Although the compressor can easily exploit ample block-level parallelism, it is much more difficult to extract such coarse-grain parallelism from the decompressor because a block boundary cannot be located until decompression of the previous block is completed. this paper presents novel algorithms to efficiently predict block boundaries and a runtime system that enables efficient block-level parallel decompression, called SDM. the SDM execution model features speculative pipelining with three stages: Scanner, Decompressor, and Merger. the scanner stage employs a high-confidence prediction algorithm that finds compressed block boundaries without fully decompressing individual blocks. this information is communicated to the parallel decompressor stage in which multiple blocks are decompressed in parallel. the decompressed blocks are merged in order by the merger stage to produce the final output. the SDM runtime is specialized to execute this pipeline correctly and efficiently on resource-constrained embedded platforms. With SDM we effectively parallelize three production-grade variable-length decompression algorithms-zlib, bzip2, and H.264-with maximum speedups of 2.50x and 8.53x (and geometric mean speedups of 1.96x and 4.04x) on 4-core and 36-core embedded platforms, respectively.

关键词： Design Performance Parallelization runtime speculation compression multicores embedded systems

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WoCA: Avoiding Intermittent Execution in embedded systems by Worst-Case Analyses with Device States 25

WoCA: Avoiding Intermittent Execution in Embedded Systems by...

引用

25th acm sigplan/sigbed International conference on languages, compilers, and tools for embedded systems (LCTES)

作者： Raffeck, Phillip Maier, Johannes Waegemann, Peter FAU Erlangen Nurnberg Erlangen Germany

ISBN: (纸本)9798400706165

embedded systems with intermittent energy supply can revolutionize the Internet of things, as they are energy self-sufficient due to energy harvesting. Existing intermittent-computing approaches, running directly from non-volatile memory, allow incremental progress of machine-code instructions. However, this progress does not apply to many devices (e.g., transceivers) having transactional (i.e., all-or-nothing) semantics: Power failures during transactions lead to starvation when frequently experiencing failed attempts. We introduce WoCA, an approach that exploits static, whole-system worst-case analysis for device-driven intermittent computing. With the currently available energy, WoCA enables transactional device uses and guarantees forward progress. WoCA's novel static analysis tracks program-path-sensitive device states and transitions to yield energy bounds. With these bounds, WoCA's runtime decides when to safely execute code between checkpoints. Using WoCA's hardware platform, we validate that WoCA makes more efficient use of available energy compared to worst-case-agnostic approaches, while also giving runtime guarantees.

关键词： static analysis intermittent systems worst-case energy consumption (WCEC) energy constraints devices

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Proceedings of the acm sigplan conference on languages, compilers, and tools for embedded systems (LCTES)

Proceedings of the ACM SIGPLAN Conference on Languages, Comp...

引用

16th acm sigplan/sigbed conference on languages, compilers, tools and theory for embedded systems, LCTES 2015

ISBN: (纸本)9781450332576

the proceedings contain 14 papers. the topics discussed include: optimizing transfers of control in the static pipeline architecture;clover: compiler directed lightweight soft error resilience;improving data access efficiency by using context-aware loads and stores;a practical getaway: applications of escape analysis in embedded real-time systems;FREE RIDER: a tool for retargeting platform-specific intrinsic functions;cross-kernel control-flow-graph analysis for event-driven real-time systems;enabling efficient alias speculation;WCET-aware dynamic D-cache locking for a single task;StarL: towards a unified framework for programming, simulating and verifying distributed robotic systems;improving the precision of abstract interpretation based cache persistence analysis;implementation-aware model analysis: the case of buffer-throughput tradeoff in streaming applications;and secure and durable (SEDURA): an integrated encryption and wear-leveling framework for PCM-based main memory.

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TinySeg: Model Optimizing Framework for Image Segmentation on Tiny embedded systems 25

TinySeg: Model Optimizing Framework for Image Segmentation o...

引用

25th acm sigplan/sigbed International conference on languages, compilers, and tools for embedded systems (LCTES)

作者： Chae, Byungchul Kim, Jiae Heo, Seonyeong Kyung Hee Univ Yongin South Korea

ISBN: (纸本)9798400706165

Image segmentation is one of the major computer vision tasks, which is applicable in a variety of domains, such as autonomous navigation of an unmanned aerial vehicle. However, image segmentation cannot easily materialize on tiny embedded systems because image segmentation models generally have high peak memory usage due to their architectural characteristics. this work finds that image segmentation models unnecessarily require large memory space with an existing tiny machine learning framework. that is, the existing framework cannot effectively manage the memory space for the image segmentation models. this work proposes TinySeg, a new model optimizing framework that enables memory-efficient image segmentation for tiny embedded systems. TinySeg analyzes the lifetimes of tensors in the target model and identifies long-living tensors. then, TinySeg optimizes the memory usage of the target model mainly with two methods: (i) tensor spilling into local or remote storage and (ii) fused fetching of spilled tensors. this work implements TinySeg on top of the existing tiny machine learning framework and demonstrates that TinySeg can reduce the peak memory usage of an image segmentation model by 39.3% for tiny embedded systems.

关键词： Tiny machine learning On-device machine learning Image segmentation embedded systems

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Optimizing Tensor Contractions for embedded Devices with Racetrack Memory Scratch-Pads 2019

Optimizing Tensor Contractions for Embedded Devices with Rac...

引用

20th International conference on languages, compilers, and tools for embedded systems (LCTES)

作者： Khan, Asif Ali Rink, Norman A. Hameed, Fazal Castrillon, Jeronimo Tech Univ Dresden Dresden Germany

ISBN: (纸本)9781450367240

Tensor contraction is a fundamental operation in many algorithms with a plethora of applications ranging from quantum chemistry over fluid dynamics and image processing to machine learning. the performance of tensor computations critically depends on the efficient utilization of on-chip memories. In the context of low-power embedded devices, efficient management of the memory space becomes even more crucial, in order to meet energy constraints. this work aims at investigating strategies for performance- and energy-efficient tensor contractions on embedded systems, using racetrack memory (RTM)-based scratch-pad memory (SPM). Compiler optimizations such as the loop access order and data layout transformations paired with architectural optimizations such as prefetching and preshifting are employed to reduce the shifting overhead in RTMs. Experimental results demonstrate that the proposed optimizations improve the SPM performance and energy consumption by 24% and 74% respectively compared to an iso-capacity SRAM.

关键词： Compiler optimization data transformation tensors tensor contraction matrix multiplication racetrack memory preshifting prefetching embedded systems

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Adaptive Optimization for OpenCL Programs on embedded Heterogeneous systems 2017

Adaptive Optimization for OpenCL Programs on Embedded Hetero...

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18th acm sigplan/sigbed conference on languages, compilers, tools and theory for embedded systems (LCTES)

作者： Taylor, Ben Marco, Vicent Sanz Wang, Zheng Univ Lancaster Sch Comp & Commun Lancaster England

ISBN: (纸本)9781450350303

Heterogeneous multi-core architectures consisting of CPUs and GPUs are commonplace in today's embedded systems. these architectures offer potential for energy efficient computing if the application task is mapped to the right core. Realizing such potential is challenging due to the complex and evolving nature of hardware and applications. this paper presents an automatic approach to map OPENCL kernels onto heterogeneous multi-cores for a given optimization criterion - whether it is faster runtime, lower energy consumption or a trade-off between them. this is achieved by developing a machine learning based approach to predict which processor to use to run the OPENCL kernel and the host program, and at what frequency the processor should operate. Instead of hand-tuning a model for each optimization metric, we use machine learning to develop a unified framework that first automatically learns the optimization heuristic for each metric off-line, then uses the learned knowledge to schedule OPENCL kernels at runtime based on code and runtime information of the program. We apply our approach to a set of representative OPENCL benchmarks and evaluate it on an ARM big. LITTLE mobile platform. Our approach achieves over 93% of the performance delivered by a perfect predictor. We obtain, on average, 1.2x, 1.6x, and 1.8x improvement respectively for runtime, energy consumption and the energy delay product when compared to a comparative heterogeneous-aware OPENCL task mapping scheme.

关键词： Heterogeneous Multi-cores Predictive Modeling Energy Efficiency OpenCL

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