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48 篇 会议

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检索条件"任意字段=14th ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems"

共 48 条记录，以下是21-30 订阅

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Efficient Implementation of Neural Networks Usual Layers on Fixed-Point Architectures 25

Efficient Implementation of Neural Networks Usual Layers on ...

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25th acm sigplan/sigbed International conference on languages, compilers, and tools for embedded systems (LCTES)

作者： Ben Khalifa, Dorra Martel, Matthieu Univ Toulouse Federat ENAC ISAE SUPAERO ONERA Toulouse France Univ Perpignan LAMPS Lab Via Domitia Perpignan France

ISBN: (纸本)9798400706165

In this article, we present a new method for implementing a neural network whose weights are floating-point numbers on a fixed-point architecture. the originality of our approach is that fixed-point formats are computed by solving an integer optimization problem derived from the neural network model and concerning the accuracy of computations and results at each point of the network. therefore, we can bound mathematically the error between the results returned by the floating-point and fixed-point versions of the network. In addition to a formal description of our method, we describe a prototype that implements it. Our tool accepts the most common neural network layers (fully connected, convolutional, max-pooling, etc.), uses an optimizing SMT solver to compute fixed-point formats and synthesizes fixed-point C code from the Tensorflow model of the network. Experimental results show that our tool is able to achieve performance while keeping the relative numerical error below the given tolerance threshold. Furthermore, the results show that our fixed-point synthesized neural networks consume less time and energy when considering a typical embedded platform using an STM32 Nucleo-144 board.

关键词： Neural Networks Code Synthesis Constraint Generation Computer Arithmetic embedded systems

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Integrating Task Scheduling and Cache Locking for Multicore Real-Time embedded systems 2017

Integrating Task Scheduling and Cache Locking for Multicore ...

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18th acm sigplan/sigbed conference on languages, compilers, tools and theory for embedded systems (LCTES)

作者： Zheng, Wenguang Wu, Hui Nie, Chuanyao Tianjin Univ Technol Tianjin Peoples R China Univ New South Wales Sydney NSW Australia

ISBN: (纸本)9781450350303

Modern embedded processors provide hardware support for cache locking, a mechanism used to facilitate the WCET (Worst-Case Execution Time) calculation of a task. We investigate the problem of integrating task scheduling and cache locking for a set of preemptible tasks with individual release times and deadlines on a multicore processor with two-level caches. We propose a novel integrated approach that schedules the task set and allocates the locked cache contents of each task to the local caches (L1 caches) and the level-two cache (L2 cache). Our approach consists of three major components, the task scheduler, the L1 cache allocator, and the L2 cache allocator. the task scheduler aims at minimizing the number of task preemptions. the L1 cache allocator converts the interference graph of all the tasks scheduled on each core into a DAG by considering the preemptions between tasks and allocates the L1 cache space to each task. the L2 cache allocator converts the interference graph of all the tasks into a DAG by using a k-longest-path-based graph orientation algorithm and allocates the L2 cache space to each task. Both cache allocators significantly improve the cache utilization for all the caches due to the efficient use of the interference graphs of tasks. We have implemented our approach and compared it with the extended version of the preemption tree-based approach and the static analysis approach without cache locking by using a set of benchmarks from the Malardalen WCET benchmark suite and SNU real-time benchmarks. Compared to the extended version of the preemption tree-based approach, the maximum WCRT (Worst Case Response Time) improvement of our approach is 15%. Compared to the static analysis approach, the maximum WCRT improvement of our approach is 37%.

关键词： Cache locking task scheduling cache allocation multicore processor

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TWFuzz: Fuzzing embedded systems with three Wires 25

TWFuzz: Fuzzing Embedded Systems with Three Wires

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25th acm sigplan/sigbed International conference on languages, compilers, and tools for embedded systems (LCTES)

作者： Feng, Zhongwen Ma, Junyan Chang Univ Sch Informat Engn Xian Peoples R China

ISBN: (纸本)9798400706165

Fuzzing is a highly effective means of discovering vulnerabilities in traditional software. However, when it comes to fuzzing an embedded system, especially for a smaller micro-controller device with monolithic firmware, the challenges are considerable. the highly constrained resources of the system and the diverse behaviors of peripherals often render software instrumentation or emulation-based fuzzing impractical in many cases. In this work, we introduce TWFuzz, a fuzzing tool designed for effective coverage collection in embedded systems. Specifically, TWFuzz relies on two hardware interfaces (tracing and debugging) and three types of probes (program counter samples, instruction address matchings, hardware breakpoints) as feedback channels for coverage-guided fuzzing. the ARM Single Wire Output (SWO) hardware tracing interface is used for capturing periodic samples of the program counter. the ARM Serial Wire Debug (SWD) debugging interface is used for setting and checking a limited number of instruction address matchings and hardware breakpoints. With these three types of probes, TWFuzz can extract coverage information without costly code instrumentation and hardware emulation, which enables effective fuzzing on embedded systems. To optimize the fuzzing flow, in particular the tracing analysis part, we implement TWFuzz on PYNQ-Z1 FPGA board. We evaluate TWFuzz on two development boards. Compared to the state-of-the-art open-source fuzzer GDBFuzz, TWFuzz's average code coverage rate is 1.24 times that of GDBFuzz.

关键词： firmware security fuzzing embedded systems ARM CoreSight

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Proceedings of the acm sigplan conference on languages, compilers, and tools for embedded systems (LCTES)

Proceedings of the ACM SIGPLAN Conference on Languages, Comp...

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19th acm sigplan/sigbed International conference on languages, compilers, and tools for embedded systems, LCTES 2018

ISBN: (纸本)9781450358033

the proceedings contain 12 papers. the topics discussed include: a memory-bounded, deterministic and terminating semantics for the synchronous programming language Ceau;MakeCode and CODAL: intuitive and efficient embedded systems programming for education;adaptive deep learning model selection on embedded systems;optimizing RAID/SSD controllers with lifetime extension for flash-based SSD array;compositionality in scenario-aware dataflow: a rendezvous perspective;decoupling address generation from loads and stores to improve data access energy efficiency;verification of coarse-grained reconfigurable arrays through random test programs;deep neural networks compiler for a trace-based accelerator;transparent standby for low-power, resource-constrained embedded systems: a programming language-based approach;statically relating program properties for efficient verification;JSCore: architectural support for accelerating JavaScript execution;and an open-source realtime computational platform.

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Proceedings of the acm sigplan conference on languages, compilers, and tools for embedded systems (LCTES)

Proceedings of the ACM SIGPLAN Conference on Languages, Comp...

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18th acm sigplan/sigbed conference on languages, compilers, and tools for embedded systems, LCTES 2017

ISBN: (纸本)9781450350303

the proceedings contain 11 papers. the topics discussed include: AOT vs. JIT: impact of profile data on code quality;adaptive optimization for OpenCL programs on embedded heterogeneous systems;auto-vectorization for image processing DSLs;dynamic translation of structured loads/stores and register mapping for architectures with SIMD extensions;optimal functional unit assignment and voltage selection for pipelined MPSoC with guaranteed probability on time performance;integrated IoT programming with selective abstraction;towards SMT-based LTL model checking of clock constraint specification language for real-time and embedded systems;integrating task scheduling and cache locking for multicore real-time embedded systems;towards memory-efficient processing-in-memory architecture for convolutional neural networks;unified nvTCAM and sTCAM architecture for improving packet matching performance;a lightweight progress maximization scheduler for non-volatile processor under unstable energy harvesting;and OSEK-V: application-specific RTOS instantiation in hardware.

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Lightweight Generics in embedded systems through Static Analysis 12

Lightweight Generics in Embedded Systems through Static Anal...

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13th acm sigplan/sigbed International conference on languages, compilers, tools and theory for embedded systems

作者： Sallenave, Olivier Ducournau, Roland Cortus Montpellier France Univ Montpellier 2 F-34095 Montpellier 5 France CNRS LIRMM F-75700 Paris France

ISBN: (纸本)9781450312127

Low-end embedded systems are still programmed in C and assembly, and adopting high-level languages such as C# should reduce the length of their development cycles. For these systems, code size is a major concern, but run-time efficiency should also be reasonable - programmers will not migrate to C# unless the overhead compared with C is insignificant. In this paper, we propose a static approach based on whole program optimization for implementing .NET generics in such systems. Indeed, the implementation of run-time generics involves a tradeoff between size and run-time efficiency. In this proposal, generic instances are detected through a generalization of RTA to parametric polymorphism. Also, we propose an implementation scheme which employs code sharing and more effective coercions than boxing. Unlike existing implementation schemes, it is scalable in the number of generic instances without involving boxing and unboxing in a systematic way.

关键词： Algorithms Experimentation languages Measurement Performance Closed-world assumption generics polymorphic recursion polymorphism subtype test type analysis

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Proceedings of the acm sigplan conference on languages, compilers, and tools for embedded systems (LCTES)

Proceedings of the ACM SIGPLAN Conference on Languages, Comp...

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17th acm sigplan/sigbed conference on languages, compilers, tools and theory for embedded systems, LCTES 2016

ISBN: (纸本)9781450343169

the proceedings contain 12 papers. the topics discussed include: efficient asynchronous interrupt handling in a full-system instruction set simulator;code cache management in managed language VMs to reduce memory consumption for embedded systems;a graph-based iterative compiler pass selection and phase ordering approach;translation validation of loop and arithmetic transformations in the presence of recurrences;loop-oriented array- and field-sensitive pointer analysis for automatic SIMD vectorization;generalized cache tiling for dataflow programs;symbolic execution for memory consumption analysis;tic: a scalable model checking based approach to WCET estimation;compensate or ignore? meeting control robustness requirements through adaptive soft-error handling;opportunity for compute partitioning in pursuit of energy-efficient systems;compiling a gesture recognition application for a low-power spatial architecture;and a machine learning approach to mapping streaming workloads to dynamic multicore processors.

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Creating Portable, Repeatable, Realistic Benchmarks for embedded systems and the Challenges thereof 12

Creating Portable, Repeatable, Realistic Benchmarks for Embe...

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13th acm sigplan/sigbed International conference on languages, compilers, tools and theory for embedded systems

作者： Gal-On, Shay Levy, Markus EEMBC

ISBN: (纸本)9781450312127

To appreciate the challenges of analysing embedded processor behaviour, step back in time to understand the evolution of embedded processors. Only a few decades ago, embedded processors were relatively simple devices (compared to today), represented by a host of 8- and 16-bit microcontrollers, and 32-bit microprocessors, with minimal integration. Today, these processors (even the so-called, low-end microcontrollers), have evolved into highly-integrated SoCs with a wide variety of architectures capable of tackling both specific and general-purpose tasks. Associated with these transformations, the benchmarks used to quantify the capabilities have also grown in complexity and range. At the simplest level, benchmarks such as CoreMark analyse the fundamental processor cores. At the other end of the spectrum, system benchmarks, such BrowsingBench, analyse the entire SoC as well as the system software stack and even the physical interfaces. this paper examines some of the challenges of applying such benchmarks, and explains the methodologies used at EEMBC to manage portability, repeatability, and realism.

关键词： Algorithms Measurement Performance Standardization Benchmark Workload Characterization Performance Analysis

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FORMLESS: Scalable Utilization of embedded Manycores in Streaming Applications 12

FORMLESS: Scalable Utilization of Embedded Manycores in Stre...

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13th acm sigplan/sigbed International conference on languages, compilers, tools and theory for embedded systems

作者： Hashemi, Matin Foroozannejad, Mohammad H. Ghiasi, Soheil Etzel, Christoph Sharif Univ Technol Tehran Iran Univ Calif Davis Davis CA 95616 USA Univ Augsburg Augsburg Germany

ISBN: (纸本)9781450312127

Variants of dataflow specification models are widely used to synthesize streaming applications for distributed-memory parallel processors. We argue that current practice of specifying streaming applications using rigid dataflow models, implicitly prohibits a number of platform oriented optimizations and hence limits portability and scalability with respect to number of processors. We motivate Functionally-cOnsistent stRucturally-MalLEabe Streaming Specification, dubbed FORMLESS, which refers to raising the abstraction level beyond fixed-structure dataflow to address its portability and scalability limitations. To demonstrate the potential of the idea, we develop a design space exploration scheme to customize the application specification to better fit the target platform. Experiments with several common streaming case studies demonstrate improved portability and scalability over conventional dataflow specification models, and confirm the effectiveness of our approach.

关键词： Dataflow Graph Stream Application embedded Manycore Processor

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Symbolic execution for memory consumption analysis 2016

Symbolic execution for memory consumption analysis

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17th acm sigplan/sigbed conference on languages, compilers, tools and theory for embedded systems, LCTES 2016

作者： Chu, Duc-Hiep Jaffar, Joxan Maghareh, Rasool National University of Singapore Singapore Singapore

ISBN: (纸本)9781450343169

With the advances in both hardware and software of embedded systems in the past few years, dynamic memory allocation can now be safely used in embedded software. As a result, the need to develop methods to avoid heap overflow errors in safety-critical embedded systems has increased. Resource analysis of imperative programs with non-regular loop patterns and signed integers, to support both memory allocation and deallocation, has long been an open problem. Existing methods can generate symbolic bounds that are parametric w.r.t. the program inputs;such bounds, however, are imprecise in the presence of non-regular loop patterns. In this paper, we present a worst-case memory consumption analysis, based upon the framework of symbolic execution. Our assumption is that loops (and recursions) of to-be-analyzed programs are indeed bounded. We then can exhaustively unroll loops and the memory consumption of each iteration can be precisely computed and summarized for aggregation. Because of path-sensitivity, our algorithm generates more precise bounds. Importantly, we demonstrate that by introducing a new concept of reuse, symbolic execution scales to a set of realistic benchmark programs. © 2016 acm.

关键词： embedded systems

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