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检索条件"任意字段=14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming"

共 382 条记录，以下是211-220 订阅

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Contention elimination by replication of sequential sections in distributed shared memory programs 01

Contention elimination by replication of sequential sections...

引用

8th acm sigplan symposium on principles and practice of parallel programming

作者： Lu, H. Cox, A.L. Zwaenepoel, W. Department of Computer Science Rice University Houston TX 77005 United States

ISBN: (纸本)9781581133462

In shared memory programs contention often occurs at the transition between a sequential and a parallel section of the code. As all threads start executing the parallel section, they often access data just modified by the thread that executed the sequential section, causing a flurry of data requests to converge on that processor. We address this problem in a software distributed shared memory system by replicating the execution of the sequential sections on all processors. Communication during this replicated sequential execution is reduced by using multicast. We have implemented replicated sequential execution with multicast support in OpenMP/NOW, a version of of OpenMP that runs on networks of workstations. We do not rely on compile-time data analysis, and therefore we can handle irregular and pointer-based applications. We show significant improvement for two pointer-based applications that suffer from severe contention without replicated sequential execution.

关键词： parallel processing systems

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PHANTOM: Predicting Performance of parallel Applications on Large-Scale parallel Machines Using a Single Node

PHANTOM: Predicting Performance of Parallel Applications on ...

引用

15th acm sigplan symposium on principles and practice of parallel programming

作者： Zhai, Jidong Chen, Wenguang Zheng, Weimin Tsinghua Univ Tsinghua Natl Lab Informat Sci & Technol Dept Comp Sci & Technol Beijing 100084 Peoples R China

ISBN: (纸本)9781605587080

For designers of large-scale parallel computers, it is greatly desired that performance of parallel applications can be predicted at the design phase. However, this is difficult because the execution time of parallel applications is determined by several factors, including sequential computation time in each process, communication time and their convolution. Despite previous efforts, it remains an open problem to estimate sequential computation time in each process accurately and efficiently for large-scale parallel applications on non-existing target machines. this paper proposes a novel approach to predict the sequential computation time accurately and efficiently. We assume that there is at least one node of the target platform but the whole target system need not be available. We make two main technical contributions. First, we employ deterministic replay techniques to execute any process of a parallel application on a single node at real speed. As a result, we can simply measure the real sequential computation time on a target node for each process one by one. Second, we observe that computation behavior of processes in parallel applications can be clustered into a few groups while processes in each group have similar computation behavior. this observation helps us reduce measurement time significantly because we only need to execute representative parallel processes instead of all of them. We have implemented a performance prediction framework, called PHANTOM, which integrates the above computation-time acquisition approach with a trace-driven network simulator. We validate our approach on several platforms. For ASCI Sweep3D, the error of our approach is less than 5% on 1024 processor cores. Compared to a recent regression-based prediction approach, PHANTOM presents better prediction accuracy across different platforms.

关键词： Performance Prediction parallel Application Deterministic Replay Trace-driven Simulation

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Combining phase identification and statistic modeling for automated parallel benchmark generation 2015

Combining phase identification and statistic modeling for au...

引用

20th acm sigplan symposium on principles and practice of parallel programming, PPoPP 2015

作者： Jin, Ye Liu, Mingliang Ma, Xiaosong Liu, Qing Logan, Jeremy Podhorszki, Norbert Choi, Jong Youl Klasky, Scott NCSU United States QCRI Qatar Oak Ridge National Lab. United States

ISBN: (纸本)9781450332057

parallel application benchmarks are indispensable for evaluating/optimizing HPC software and hardware. However, it is very challenging and costly to obtain high-fidelity benchmarks reflecting the scale and complexity of state-of-the-art parallel applications. Hand-extracted synthetic benchmarks are time- and labor-intensive to create. Real applications themselves, while offering most accurate performance evaluation, are expensive to compile, port, reconfigure, and often plainly inaccessible due to security or ownership concerns. this work contributes APPRIME, a novel tool for trace-based automatic parallel benchmark generation. Taking as input standard communication-I/O traces of an application's execution, it couples accurate automatic phase identification with statistical regeneration of event parameters to create compact, portable, and to some degree reconfigurable parallel application benchmarks. Experiments with four NAS parallel Benchmarks (NPB) and three real scientific simulation codes confirm the fidelity of APPRIME benchmarks. they retain the original applications' performance characteristics, in particular the relative performance across platforms.

关键词： Benchmarking

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Flattening and parallelizing irregular, recurrent loop nests 95

Flattening and parallelizing irregular, recurrent loop nests

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Proceedings of the 5th acm sigplan symposium on principles and practice of parallel programming

作者： Ghuloum, Anwar M. Fisher, Allan L. Carnegie Mellon Univ Pittsburgh PA United States

ISBN: (纸本)9780897917001

Irregular loop nests in which the loop bounds are determined dynamically by indexed arrays are difficult to compile into expressive parallel constructs, such as segmented scans and reductions. In this paper, we describe a suite of transformations to automatically parallelize such irregular loop nests, even in the presence of recurrences. We describe a simple, general loop flattening transformation, along with new optimizations which make it a viable compiler transformation. A robust recurrence parallelization technique is coupled to the loop flattening transformation, allowing parallelization of segmented reductions, scans, and combining-sends over arbitrary associative operators. We discuss the implementation and performance results of the transformations in a parallelizing Fortran 77 compiler for the Cray C90 supercomputer. In particular, we focus on important sparse matrix-vector multiplication kernels, for one of which we are able to automatically derive an algorithm used by one of the fastest library routines available.

关键词： parallel processing systems

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Cilk: An efficient multithreaded runtime system

Cilk: An efficient multithreaded runtime system

引用

Proceedings of the 5th acm sigplan symposium on principles and practice of parallel programming

作者： Blumofe, Robert D. Joerg, Christopher F. Kuszmaul, Bradley C. Leiserson, Charles E. Randall, Keith H. Zhou, Yuli MIT Lab for Computer Science Cambridge United States

Cilk (pronounced `silk') is a C-based runtime system for multi-threaded parallel programming. In this paper, we document the efficiency of the Cilk work-stealing scheduler, both empirically and analytically. We show that on real and synthetic applications, the `work' and `critical path' of a Cilk computation can be used to accurately model performance. Consequently, a Cilk programmer can focus on reducing the work and critical path of his computation, insulated from load balancing and other runtime scheduling issues. We also prove that for the class of `fully strict' (well-structured) programs, the Cilk scheduler achieves space, time, and communication bounds all within a constant factor of optimal. the Cilk runtime system currently runs on the Connection Machine CM5 MPP, the Intel Paragon MPP, the Silicon Graphics Power Challenge SMP, and the MIT Phish network of workstations. Applications written in Cilk include protein folding, graphic rendering, backtrack search, and the Socrates chess program, which won third prize in the 1994 acm International Computer Chess Championship.

关键词： parallel processing systems

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Array operation synthesis scheme to optimize Fortran 90 programs

Array operation synthesis scheme to optimize Fortran 90 prog...

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Proceedings of the 5th acm sigplan symposium on principles and practice of parallel programming

作者： Hwang, Gwan-Hwan Lee, Jenq Kuen Ju, Dz-Ching Natl Tsing-Hua Univ Taiwan

An increasing number of programming languages, such as Fortran 90 and APL, are providing a rich set of intrinsic array functions and array expressions. these constructs which constitute an important part of data parallel languages provide excellent opportunities for compiler optimizations. In this paper, we present a new approach to combine consecutive data access patterns of array constructs into a composite access function to the source arrays. Our scheme is based on the composition of access functions, which is similar to a composition of mathematic functions. Our new scheme can handle not only data movements of arrays of different numbers of dimensions and segmented array operations but also masked array expressions and multiple sources array operations. As a result, our proposed scheme is the first synthesis scheme which can synthesize Fortran 90 RESHAPE, EOSHIFT, MERGE, and WHERE constructs together. Experimental results show speedups from 1.21 to 2.95 for code fragments from real applications on a Sequent multiprocessor machine by incorporating the proposed optimizations.

关键词： FORTRAN (programming language)

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Scalable parallel Debugging with Statistical Assertions

Scalable Parallel Debugging with Statistical Assertions

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17th acm sigplan symposium on principles and practice of parallel programming

作者： Minh Ngoc Dinh Abramson, David Jin, Chao Gontarek, Andrew Moench, Bob DeRose, Luiz Monash Univ Clayton Vic 3800 Australia Cray Inc St Paul MN 55101 USA

Traditional debuggers are of limited value for modern scientific codes that manipulate large complex data structures. this paper discusses a novel debug-time assertion, called a "Statistical Assertion", that allows a user to reason about large data structures, and the primitives are parallelised to provide an efficient solution. We present the design and implementation of statistical assertions, and illustrate the debugging technique with a molecular dynamics simulation. We evaluate the performance of the tool on a 12,000 cores Cray XE6.

关键词： Performance Verification parallel debugging statistic assertion

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PiPAD: Pipelined and parallel Dynamic GNN Training on GPUs 23

PiPAD: Pipelined and Parallel Dynamic GNN Training on GPUs

引用

28th acm sigplan Annual symposium on principles and practice of parallel programming, PPoPP 2023

作者： Wang, Chunyang Sun, Desen Bai, Yuebin Beihang University Beijing China

ISBN: (纸本)9798400700156

Dynamic Graph Neural Networks (DGNNs) have been widely applied in various real-life applications, such as link prediction and pandemic forecast, to capture both static structural information and temporal characteristics from dynamic graphs. Combining both time-dependent and -independent components, DGNNs manifest substantial parallel computation and data reuse potentials, but suffer from severe memory access inefficiency and data transfer overhead under the canonical one-graph-at-a-time training pattern. To tackle these challenges, we propose PiPAD, a Pipelined and parallel DGNN training framework for the end-to-end performance optimization on GPUs. From both algorithm and runtime level, PiPAD holistically reconstructs the overall training paradigm from the data organization to computation manner. Capable of processing multiple graph snapshots in parallel, PiPAD eliminates unnecessary data transmission and alleviates memory access inefficiency to improve the overall performance. Our evaluation across various datasets shows PiPAD achieves 1.22 × - 9.57× speedup over the state-of-the-art DGNN frameworks on three representative models. © 2023 acm.

关键词： Memory architecture

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Managing application parallelism via parallel efficiency regulation 19

Managing application parallelism via parallel efficiency reg...

引用

24th acm sigplan symposium on principles and practice of parallel programming, PPoPP 2019

作者： Srikanthan, Sharanyan Ferro, Princeton Chakraborti, Sayak Dwarkadas, Sandhya University of Rochester United States

ISBN: (纸本)9781450362252

Modern multiprocessor systems contain a wealth of compute, memory, and communication network resources, such that multiple applications can often successfully execute on and compete for these resources. Unfortunately, good performance for individual applications in addition to achieving overall system eficiency proves a dificult task, especially for applications with low parallel eficiency (speedup per utilized computational core). Limitations to parallel eficiency arise out of factors such as algorithm design, excess synchronization, limitations in hardware resources, and sub-optimal task placement on CPUs. In this work, we introduce MAPPER, a Manager of Application parallelism via parallel Efficiency Regulation. MAPPER monitors and coordinates all participating applications by making two coupled decisions: how much parallelism to afford to each application, and which specific CPU cores to schedule applications on. While MAPPER can work for generic applications without modifying their parallel runtimes, we introduce a simple interface that can be used by parallel runtime systems for a tighter integration, resulting in better task granularity control. Using MAPPER can result in up to 3.3X speedup, with an average performance improvement of 20%. © 2019 Copyright held by the owner/author(s).

关键词： Program processors

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Does Cache Sharing on Modern CMP Matter to the Performance of Contemporary Multithreaded Programs?

Does Cache Sharing on Modern CMP Matter to the Performance o...

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15th acm sigplan symposium on principles and practice of parallel programming

作者： Zhang, Eddy Z. Jiang, Yunlian Shen, Xipeng Coll William & Mary Dept Comp Sci Williamsburg VA 23187 USA

ISBN: (纸本)9781605587080

Most modern Chip Multiprocessors (CMP) feature shared cache on chip. For multithreaded applications, the sharing reduces communication latency among co-running threads, but also results in cache contention. A number of studies have examined the influence of cache sharing on multithreaded applications, but most of them have concentrated on the design or management of shared cache, rather than a systematic measurement of the influence. Consequently, prior measurements have been constrained by the reliance on simulators, the use of out-of-date benchmarks, and the limited coverage of deciding factors. the influence of CMP cache sharing on contemporary multithreaded applications remains preliminarily understood. In this work, we conduct a systematic measurement of the influence on two kinds of commodity CMP machines, using a recently released CMP benchmark suite, PARSEC, with a number of potentially important factors on program, OS, and architecture levels considered. the measurement shows some surprising results. Contrary to commonly perceived importance of cache sharing, neither positive nor negative effects from the cache sharing are significant for most of the program executions, regardless of the types of parallelism, input datasets, architectures, numbers of threads, and assignments of threads to cores. After a detailed analysis, we find that the main reason is the mismatch of current development and compilation of multithreaded applications and CMP architectures. By transforming the programs in a cache-sharing-aware manner, we observe up to 36% performance increase when the threads are placed on cores appropriately.

关键词： Shared Cache thread Scheduling parallel Program Optimizations Chip Multiprocessors

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