检索结果-内蒙古大学图书馆

29th acm sigplan Annual symposium on principles and practice of parallel programming, PPoPP 2024

作者： Liu, Quanquan C. Shun, Julian Zablotchi, Igor Yale University United States MIT CSAIL United States Mysten Labs Switzerland

ISBN: (纸本)9798400704352

Maintaining a dynamic k-core decomposition is an important problem that identifies dense subgraphs in dynamically changing graphs. Recent work by Liu et al. [SPAA 2022] presents a parallel batch-dynamic algorithm for maintaining an approximate k-core decomposition. In their solution, both reads and updates need to be batched, and therefore each type of operation can incur high latency waiting for the other type to finish. To tackle most real-world workloads, which are dominated by reads, this paper presents a novel hybrid concurrent-parallel dynamic k-core data structure where asynchronous reads can proceed concurrently with batches of updates, leading to significantly lower read latencies. Our approach is based on tracking causal dependencies between updates, so that causally related groups of updates appear atomic to concurrent readers. Our data structure guarantees linearizability and liveness for both reads and updates, and maintains the same approximation guarantees as prior work. Our experimental evaluation on a 30-core machine shows that our approach reduces read latency by orders of magnitude compared to the batch-dynamic algorithm, up to a (4.05 · 105 ) -factor. Compared to an unsynchronized (non-linearizable) baseline, our read latency overhead is only up to a 3.21-factor greater, while improving accuracy of coreness estimates by up to a factor of 52.7. © 2024 Copyright held by the owner/author(s).

关键词： Data structures

来源：评论

学校读者我要写书评

暂无评论

Exploiting task-level concurrency in a programmable network interface

引用

acm sigplan NOTICES 2003年第10期38卷 61-72页

作者： Kim, HY Pai, VS Rixner, S Rice Univ Houston TX 77251 USA

Programmable network interfaces provide the potential to extend the functionality of network services but lead to instruction processing overheads when compared to application-specific network interfaces. this paper aims to offset those performance disadvantages by exploiting task-level concurrency in the workload to parallelize the network interface firmware for a programmable controller with two processors. By carefully partitioning the handler procedures that process various events related to the progress of a packet, the system can minimize sharing, achieve load balance, and efficiently utilize on-chip storage. Compared to the uniprocessor firmware released by the manufacturer, the parallelized network interface firmware increases throughput by 65% for bidirectional UDP traffic of maximum-sized packets, 157% for bidirectional UDP traffic of minimum-sized packets, and 32-107% for real network services. this parallelization results in performance within 10-20% of a modem ASIC-based network interface for real network services.

关键词： experimentation, performance programmable network interface parallel programming ethernet firmware

来源：评论

学校读者我要写书评

暂无评论

Basic compiler algorithms for parallel programs

Proceedings of the ACM SIGPLAN Symposium on Principles and P...

引用

Proceedings of the acm sigplan symposium on principles and practice of parallel programming, PPOPP 1999年 1-12页

作者： Lee, Jaejin Padua, David A. Midkiff, Samuel P. Univ of Illinois Urbana United States

Traditional compiler techniques developed for sequential programs do not guarantee the correctness (sequential consistency) of compiler transformations when applied to parallel programs. this is because traditional compilers for sequential programs do not account for the updates to a shared variable by different threads. We present a concurrent static single assignment (CSSA) form for parallel programs containing cobegin/coend and parallel do constructs and post/wait synchronization primitives. Based on the CSSA form, we present copy propagation and dead code elimination techniques. Also, a global value numbering technique that detects equivalent variables in parallel programs is presented. By using global value numbering and the CSSA form, we extend classical common subexpression elimination, redundant load/store elimination, and loop invariant detection to parallel programs without violating sequential consistency. these optimization techniques are the most commonly used techniques for sequential programs. By extending these techniques to parallel programs, we can guarantee the correctness of the optimized program and maintain single processor performance in a multiprocessor environment.

关键词： parallel processing systems

来源：评论

学校读者我要写书评

暂无评论

Compactly representing parallel program executions

引用

acm sigplan NOTICES 2003年第10期38卷 190-201页

作者： Goel, A Roychoudhury, A Mitra, T Natl Univ Singapore Sch Comp Singapore 117543 Singapore

Collecting a program's execution profile is important for many reasons: code optimization, memory layout, program debugging and program comprehension. Path based execution profiles are more detailed than count based execution profiles, since they present the order of execution of the various blocks in a program: modules, procedures, basic blocks etc. Recently, online string compression techniques have been employed for collecting compact representations of sequential program executions. In this paper, we show how a similar approach can be taken for shared memory parallel programs. Our compaction scheme yields one to two orders of magnitude compression compared to the uncompressed parallel program trace on some of the SPLASH benchmarks. Our compressed execution traces contain detailed information about synchronization and control/data flow which can be exploited for post-mortem analysis. In particular, information in our compact execution traces are useful for accurate data race detection (detecting unsynchronized shared variable accesses that occurred in the execution).

关键词： algorithms measurement path profiling program path compression dynamic program analysis

来源：评论

学校读者我要写书评

暂无评论

Teaching parallel Design Patterns to Undergraduates in Computer Science 14

Teaching Parallel Design Patterns to Undergraduates in Compu...

引用

45th acm SIGCSE Technical symposium on Computer Science Education (SIGCSE)

作者： Brown, Richard A. Adams, Joel C. Ferner, Clayton Shoop, Elizabeth Wilkinson, Barry St Olaf Coll Northfield MN 55057 USA Calvin Coll Grand Rapids MI 49506 USA UNC Wilmington Wilmington NC USA Macalester Coll St Paul MN 55105 USA UNC Charlotte Charlotte NC USA

ISBN: (纸本)9781450326056

the industry shift emerging forms of parallel and distributed computing (PDC), including multi-core CPUs, cloud computing, and general-purpose use of GPUs, have naturally led to increased presence of PDC elements undergraduate Computer Science curriculum recommendations, such as the new and substantial "PD" knowledge area in the joint acm/IEEE CS2013 recommendations[1]. How can undergraduate students grasp the extensive and complex range of PDC principles and practices, and apply that knowledge in problem solving, while PDC technologies continue to evolve rapidly? parallel design patterns are descriptions of effective solutions to recurring parallel programming problems in particular contexts and have emerged from long-standing industry practice. parallel patterns occur at all computational levels, ranging from low-level concurrent execution patterns (such as message passing or thread pool patterns) to high-level software design patterns suitable for organizing entire systems or their components (such as model-view-control or pipe and filter patterns). the sheer number of parallel patterns, which reflect the full breadth and complexity of PDC, can be quite daunting for a newcomer. However, the ubiquity of parallel patterns in all forms of parallel and distributed computation makes these patterns relevant and illuminating at all undergraduate levels. Knowledge of parallel patterns, being reusable elements of parallel design, guides problem-solving during the creation of parallel programs;and those enduring design patterns remain relevant and useful as new PDC infrastructure emerges in this rapidly evolving field. this panel presents four viewpoints representing various approaches for teaching parallel patterns to CS undergraduates at multiple academic levels. Moderator Dick Brown co-directs (with Adams and Shoop) the CSinparallel project (***), which produces and shares modular materials for incrementally adding parallelism to existing undergraduate comp

关键词： parallel computing parallelism distributed computing education parallel design patterns curriculum design patterns Seeds Paraguin patternlets exemplars

来源：评论

学校读者我要写书评

暂无评论

Automatic parallelization of divide and conquer algorithms

Proceedings of the ACM SIGPLAN Symposium on Principles and P...

引用

Proceedings of the acm sigplan symposium on principles and practice of parallel programming, PPOPP 1999年 72-83页

作者： Rugina, Radu Rinard, Martin Massachusetts Inst of Technology Cambridge United States

Divide and conquer algorithms are a good match for modern parallel machines: they tend to have large amounts of inherent parallelism and they work well with caches and deep memory hierarchies. But these algorithms pose challenging problems for parallelizing compilers. they are usually coded as recursive procedures and often use pointers into dynamically allocated memory blocks and pointer arithmetic. All of these features are incompatible with the analysis algorithms in traditional parallelizing compilers. this paper presents the design and implementation of a compiler that is designed to parallelize divide and conquer algorithms whose subproblems access disjoint regions of dynamically allocated arrays. the foundation of the compiler is a flow-sensitive, context-sensitive, and interprocedural pointer analysis algorithm. A range of symbolic analysis algorithms build on the pointer analysis information to extract symbolic bounds for the memory regions accessed by (potentially recursive) procedures that use pointers and pointer arithmetic. the symbolic bounds information allows the compiler to find procedure calls that can execute in parallel without violating the data dependences. the compiler generates code that executes these calls in parallel. We have used the compiler to parallelize several programs that use divide and conquer algorithms. Our results show that the programs perform well and exhibit good speedup.

关键词： parallel processing systems

来源：评论

学校读者我要写书评

暂无评论

Predictive analysis of a wavefront application using LogGP

Proceedings of the ACM SIGPLAN Symposium on Principles and P...

引用

Proceedings of the acm sigplan symposium on principles and practice of parallel programming, PPOPP 1999年 141-150页

作者： Sundaram-Stukel, David Vernon, Mary K. Epic Systems Corp Madison WI United States

this paper develops a highly accurate LogGP model of a complex wavefront application that uses MPI communication on the IBM SP/2. Key features of the model include: (1) elucidation of the principal wavefront synchronization structure, and (2) explicit high-fidelity models of the MPI-send and MPI-receive primitives. the MPI-send/receive models are used to derive L, o, and G from simple two-node micro-benchmarks. Other model parameters are obtained by measuring small application problem sizes on four SP nodes. Results show that the LogGP model predicts, in seconds and with a high degree of accuracy, measured application execution time for large problems running on 128 nodes. Detailed performance projections are provided for very large future processor configurations that are expected to be available to the application developers. these results indicate that scaling beyond one or two thousand nodes yields greatly diminished in execution time, and that synchronization delays are a principal factor limiting the scalability of the application.

关键词： parallel processing systems

来源：评论

学校读者我要写书评

暂无评论

SUIF Explorer: An interactive and interprocedural parallelizer

Proceedings of the ACM SIGPLAN Symposium on Principles and P...

引用

Proceedings of the acm sigplan symposium on principles and practice of parallel programming, PPOPP 1999年 37-48页

作者： Liao, Shih-Wei Diwan, Amer Bosch Jr., Robert P. Ghuloum, Anwar Lam, Monica S. Stanford Univ United States

the SUIF Explorer is an interactive parallelization tool that is more effective than previous systems in minimizing the number of lines of code that require programmer assistance. First, the interprocedural analyses in the SUIF system is successful in parallelizing many coarse-grain loops, thus minimizing the number of spurious dependences requiting attention. Second, the system uses dynamic execution analyzers to identify those important loops that are likely to be parallelizable. third, the SUIF Explorer is the first to apply program slicing to aid programmers in interactive parallelization. the system guides the programmers in the parallelization process using a set of sophisticated visualization technique. this paper demonstrates the effectiveness of the SUIF Explorer with three case studies. the programmer was able to speed up all three programs by examining only a small fraction of the program and privatizing a few variables.

关键词： parallel processing systems

来源：评论

学校读者我要写书评

暂无评论

Stackthreads/MP: Integrating futures into calling standards

Proceedings of the ACM SIGPLAN Symposium on Principles and P...

引用

Proceedings of the acm sigplan symposium on principles and practice of parallel programming, PPOPP 1999年 60-71页

作者： Taura, Kenjiro Tabata, Kunio Yonezawa, Akinori Univ of Tokyo Tokyo Japan

An implementation scheme of fine-grain multithreading that needs no changes to current calling standards for sequential languages and modest extensions to sequential compilers is described. Like previous similar systems, it performs an asynchronous call as if it were an ordinary procedure call, and detaches the callee from the caller when the callee suspends or either of them migrates to another processor. Unlike previous similar systems, it detaches and connects arbitrary frames generated by off-the-shelf sequential compilers obeying calling standards. As a consequence, it requires neither a frontend preprocessor nor a native code generator that has a builtin notion of parallelism. the system practically works with unmodified GNU C compiler (GCC). Desirable extensions to sequential compilers for guaranteeing portability and correctness of the scheme are clarified and claimed modest. Experiments indicate that sequential performance is not sacrificed for practical applications and both sequential and parallel performance are comparable to Cilk, whose current implementation requires a fairly sophisticated preprocessor to C. these results show that efficient asynchronous calls (a.k.a. future calls) can be integrated into current calling standard with a very small impact both on sequential performance and compiler engineering.

关键词： parallel processing systems

来源：评论

学校读者我要写书评

暂无评论

Evaluation of predicated array data-flow analysis for automatic parallelization

Proceedings of the ACM SIGPLAN Symposium on Principles and P...

引用

Proceedings of the acm sigplan symposium on principles and practice of parallel programming, PPOPP 1999年 84-95页

作者： Moon, Sungdo Hall, Mary W. Univ of Southern California Marina del Rey United States

this paper presents an evaluation of a new analysis for parallelizing compilers called predicated array data-flow analysis. this analysis extends array data-flow analysis for parallelization and privatization to associate predicates with data-flow values. these predicates can be used to derive conditions under which dependences can be eliminated or privatization is possible. these conditions can be used both to enhance compile-time analysis and to introduce run-time tests that guard safe execution of a parallelized version of a computation. As compared to previous work that combines predicates with array data-flow analysis, our approach is distinguished by two features: (1) it derives low-cost, run-time parallelization tests;and, (2) it incorporates predicate embedding and predicate extraction, which translate between the domain of predicates and data-flow values to derive more precise analysis results. We present extensive experimental results across three benchmark suites and one additional program, demonstrating that predicated array data-flow analysis parallelizes more than 40% of the remaining inherently parallel loops left unparallelized by the SUIF compiler and that it yields improved speedups for 5 programs.

关键词： parallel processing systems

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：