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检索条件"任意字段=14th International Conference on Field-Programmable Logic and Applications"

共 3172 条记录，以下是171-180 订阅

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CFSA: An Efficient CPU-FPGA Synergies Accelerator for Neural Radiation field Rendering

CFSA: An Efficient CPU-FPGA Synergies Accelerator for Neural...

引用

international conference on field programmable logic and applications

作者： Shangrong Li Kai Liu Wei Liu Zibo Guo School of Computer Science and Technology Xidian University Xi’an China Smart Earth Key Laboratory Beijing China

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Neural Radiance fields (NeRF) have great potential applications in 3D spatial modeling, scene reconstruction, and related fields, such as AR/VR. However, the compute-intensive and memory-intensive characteristics of NeRF present significant obstacles for real-time applications. therefore, this work presents CFSA, a CPU-FPGA synergies hardware accelerator that enhances the deployment of NeRF in resource-constrained environments. A multilayer perceptron (MLP) processor has been designed on an FPGA with 89% utilization for the multi-resolution hash encoding NeRF algorithm. Additionally, a grid occupancy and early termination computation unit has been created, which reduces computational effort by over $\mathbf{9 0 \%}$. An overall pipeline scheduling scheme for the CPU and FPGA has also been designed. the experimental data shows that the accelerator can render synthetic data at 7.1 FPS on the Xilinx VC709 board with 100 MHz. Compared to ICARUS, a specialized architecture for NeRF-based rendering, there is a $338.1 \times$ speed improvement and a $8.4 \times$ increase in energy. Compared to the GTX 1080 Ti GPU, there is a $1.3 \times$ speed improvement and a $20.2 \times$ increase in energy.

关键词： Solid modeling three-dimensional displays Processor scheduling Computational modeling Computer architecture Neural radiance field Rendering (computer graphics) Real-time systems field programmable gate arrays Synthetic data

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Optimized Task Mapping for Inkjet Printer Pixel Data Transmission Based on Improved Particle Swarm Optimization Algorithm

Optimized Task Mapping for Inkjet Printer Pixel Data Transmi...

引用

Advanced Algorithms and Control Engineering (ICAACE), international conference on

作者： Huizi Wu Chen Li Yong Yin School of Information Engineering Wuhan University of Technology Wuhan China

ISBN: (数字)9798331535087

ISBN: (纸本)9798331535094

Inkjet printers are integral to various industries, offering high-quality printing solutions. In inkjet printing applications, field programmable gate arrays (FPGAs), composed of configurable logic blocks (CLBs), play a critical role by providing the flexibility and computational power necessary for executing complex tasks. However, conventional task mapping methods to CLBs often fail to account for communication costs, which can impair system efficiency. this paper proposes an optimization approach for task mapping based on the Similarity-Aware Gaussian Particle Swarm Optimization (SAG-PSO) algorithm, aiming to enhance mapping efficiency while minimizing communication overhead. the SAG-PSO algorithm incorporates a similarity-aware Gaussian mutation strategy and additional search iterations, improving global exploration and reducing the risk of local optima. Experimental results show that SAG-PSO outperforms traditional task mapping methods, achieving significant reductions in communication costs and improvements in task mapping efficiency. this work advances embedded systems optimization and provides a foundation for future improvements in FPGA-based task mapping strategies.

关键词： Costs Embedded systems programmable logic arrays logic gates Ink jet printing Printers Data communication Particle swarm optimization Optimization field programmable gate arrays

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Resource-Efficient 64-Bit Karatsuba Multiplier using LUTs and DSP Slices

Resource-Efficient 64-Bit Karatsuba Multiplier using LUTs an...

引用

international conference on Computer applications and Industrial Electronics (ICCAIE)

作者： Shakirah Hashim Nur Farraliza Mansor School of Computing Sciences College of Computing Informatics and Mathematics Universiti Teknologi MARA Shah Alam Malaysia

ISBN: (数字)9798350348798

ISBN: (纸本)9798350348804

Modern field programmable Gate Array (FPGA) is now equipped with Digital Signal Processing (DSP) block for faster computation. this feature can be exploited to speed-up the multiplication process which is widely needed during encryption. However, the operand size of DSP multipliers are asymmetric, 24 x 17 bits, thus complicates the multiplication process. As DSP has high-throughput function, it must be optimally used to avoid resource waste. thus, 64-bit Karatsuba multiplier is proposed in this paper to exploit the DSP advancement, based on two optimizations: operand decomposition and operand arrangement. Both optimizations are tailored to the DSP asymmetric multiplier architecture. the proposed design is implemented on Kintex 7. We only utilized 8 DSP slices and several slices of LUTs resource, smaller than non-standard tiling Karatsuba. In fact, we achieved higher DSP efficiency (97.6%) as each DSP slice is optimally utilized.

关键词： Industrial electronics Array signal processing Digital signal processing Computer architecture logic gates Table lookup Encryption

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DynaRapid: Fast-Tracking from C to Routed Circuits

DynaRapid: Fast-Tracking from C to Routed Circuits

引用

international conference on field programmable logic and applications

作者： Andrea Guerrieri Srijeet Guha Chris Lavin Eddie Hung Lana Josipović Paolo Ienne School of Engineering HES-SO Valais-Wallis Sion Switzerland School of Computer and Communication Sciences EPFL Lausanne Switzerland AMD Research and Advanced Development Department of Information Technology and Electrical Engineering ETH Zurich Zurich Switzerland

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Advancements in design automation technologies, such as high-level synthesis (HLS), have raised the input abstraction level and made the design entry process for FPGAs more friendly to software programmers. In contrast, the backend compilation process for implementing designs on FPGAs is considerably more lengthy compared to software compilation: while software code compilation may take just a few seconds, FPGA compilation times can often span from several minutes to hours due to the complexity of the underlying toolchain and ever-growing device capacities. In this paper, we present DynaRapid, a fast compilation tool that generates—in a matter of seconds—fully legal placed-and-routed designs for commercial FPGAs. Elastic circuits created by the HLS tool Dynamatic are made exclusively of a limited number of reusable components; we exploit this fact to create a library of placed and routed building blocks, and then stitch together instances of them as needed through RapidWright. Our approach accelerates the C-to-FPGA implementation process by a geomean $20 \times$ with only 10% of degradation in operating frequency compared to a conventional commercial off-the-shelf implementation flow.

关键词： Degradation Codes Design automation Law Circuits Software Libraries logic field programmable gate arrays Standards

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CFEACT: A CGRA-based Framework Enabling Agile CNN and Transformer Accelerator Design

CFEACT: A CGRA-based Framework Enabling Agile CNN and Transf...

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international conference on field programmable logic and applications

作者： Yiqing Mao Xuchen Gao Jiahang Lou Yunhui Qiu Wenbo Yin Wai-Shing Luk Lingli Wang State Key Laboratory of ASIC and System Fudan University Shanghai China

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Convolutional neural networks (CNNs) and transformer neural networks have been adopted in a wide range of applications such as natural language processing and computer vision. Coarse-grained reconfigurable architectures (CGRAs) are highly suitable for CNN and transformer applications due to their high flexibility and energy efficiency. However, current implementations of CGRA for CNNs and transformers have several limitations including the lack of System-on-Chip (SoC), insufficient support for nonlinear functions and the absence of a software toolchain. To address these challenges, we present CFEACT, a CGRA-based framework that enables agile development of CNN and transformer accelerators. CFEACT offers a broad design space of efficient CGRA accelerators through a highly flexible architecture template. the well-designed SoC, innovative mapping schemes, and comprehensive software toolchain offer a complete solution for implementing various CNN and transformer models on the generated CGRAs. Compared with the state-of-the-art works, accelerators generated by CFEACT can achieve more than $2 \times$ improvement in area-delay product for CNNs and an average of $2 \times$ higher performance for transformers.

关键词： Neural networks Transformers Software Hardware Natural language processing System-on-chip Space exploration Reconfigurable architectures Convolutional neural networks logic

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IMAGine: An In-Memory Accelerated GEMV Engine Overlay

IMAGine: An In-Memory Accelerated GEMV Engine Overlay

引用

international conference on field programmable logic and applications

作者： Md Arafat Kabir Tendayi Kamucheka Nathaniel Fredricks Joel Mandebi Jason Bakos Miaoqing Huang David Andrews Department of Electrical Engineering and Computer Science University of Arkansas Advanced Micro Devices Inc. (AMD) Department of Computer Science and Engineering University of South Carolina

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Processor-in-Memory (PIM) overlays and alternative reconfigurable tile fabrics have been proposed to eliminate the von Neumann bottleneck and enable processing performance to scale with BRAM capacity. the performance of these FPGA-based PIM architectures has been limited due to a reduction of the BRAMs maximum clock frequencies and less than ideal scaling of processing elements with increased BRAM capacity. this paper presents IMAGine, an In-Memory Accelerated GEMV engine, a PIM-array accelerator that clocks at the maximum frequency of the BRAM and scales to 100% of the available BRAMs. Comparative analyses are presented showing execution speeds over existing PIM-based GEMV engines on FPGAs and achieving a $2.65 \times-3.2 \times$ faster clock. An AMD Alveo U55 implementation is presented that achieves a system clock speed of 737 MHz, providing 64 K bit-serial multiply-accumulate (MAC) units for GEMV operation. this establishes IMAGine as the fastest PIM-based GEMV overlay, outperforming even the custom PIM-based FPGA accelerators reported to date. Additionally, it surpasses TPU v1-v2 and Alibaba Hanguang 800 in clock speed while offering an equal or greater number of multiply-accumulate (MAC) units.

关键词： Fabrics logic Engines field programmable gate arrays logic arrays Clocks

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An Improvement of A Lightweight NFC Authentication Algorithm Based on Modified Hash Function 14

An Improvement of A Lightweight NFC Authentication Algorithm...

引用

14th international conference on Information and Communication Technology Convergence, ICTC 2023

作者： Hwang, Min-Shiang Li, Hou-Wen Yang, Cheng-Ying Asia University Department of Computer Science and Information Engineering Taichung354 Taiwan Asia University The Ph.D. Program in Artificial Intelligence Taichung354 Taiwan University of Taipei Department of Computer Science Taipei Taiwan

ISBN: (纸本)9798350313277

In NFC applications, user privacy information must be protected first. Cao and Liu recently proposed a lightweight NFC authentication scheme based on an improved hash function to ensure that the user's private information will not be leaked. Although their method is highly efficient and has Mutual Authentication, Forward Security, Backward Security, and security against attacks such as Replay, Location, and Fake, once out of synchronization occurs, the method must reestablish synchronization data. therefore, this article will propose a lightweight synchronization method. © 2023 IEEE.

关键词： authentication algorithm hash function near field communication privacy

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Exploring the Resiliency of Hardware CNN for Aerospace Application

Exploring the Resiliency of Hardware CNN for Aerospace Appli...

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international conference on Synthesis, Modeling, Analysis and Simulation Methods and applications to Circuit Design (SMACD)

作者： Corrado De Sio Giorgio Cora Sarah Azimi Eleonora Vacca Luca Sterpone Dipartimento di Automatica e Informatica Politecnico di Torino Turin Italy

ISBN: (数字)9798350351927

ISBN: (纸本)9798350351934

As CNNs gain traction on hardware accelerators, field programmable Gate Arrays (FPGAs) stand out for their flexibility and computational power. However, ensuring the reliability on FPGAs poses a challenge. this study focuses on conducting a precise reliability analysis at the neuron level and implementing a selective mitigation technique to enhance CNN reliability. the Xilinx Zynq-7020 SoC is utilized to implement the ZFnet CNN, validating the proposed analysis and mitigation approach.

关键词： Prevention and mitigation Neurons logic gates Robustness Circuit synthesis Convolutional neural networks Integrated circuit modeling field programmable gate arrays Hardware acceleration Resilience

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A Software-programmable Neural Processing Unit for Graph Neural Network Inference on FPGAs

A Software-Programmable Neural Processing Unit for Graph Neu...

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international conference on field programmable logic and applications

作者： Taikun Zhang Andrew Boutros Sergey Gribok Kwadwo Boateng Vaughn Betz Department of Electrical and Computer Engineering University of Toronto Toronto ON Canada Programmable Solutions Group Intel Corporation

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Graph neural networks (GNNs) are a widely-used class of deep learning (DL) models for learning latent representations of graph-structured data for a variety of node/graph-level prediction tasks, some of which require real-time low latency inference. Most existing GNN accelerators rely on preprocessing input graphs on a host/embedded CPU to parallelize computations on different sub-graphs, making them unsuitable for real-time use cases. Others are extremely specialized streaming pipelines for only a specific type of GNN and therefore suffer from long FPGA bitstream compile times when the model is updated and cannot be used in applications that combine GNNs with other classes of DL models. In this work, we enhance the neural processing unit (NPU) FPGA overlay architecture, instruction set, and software stack to support a variety of GNN models. We achieve this without sacrificing the NPU flexibility; our enhanced NPU can be programmed purely through software to accelerate different GNNs or any of its originally supported DL workloads (e.g. MLPs, RNNs, GRUs, LSTMs). In addition, this flexibility enables our NPU software compiler to generate GNN kernels with different performance targets (throughput-optimized vs. latency-optimized) by exploiting different dimensions of compute parallelism on the same overlay architecture. Besides the flexibility benefits, our NPU implemented on an Intel Stratix 10 NX (14 nm) FPGA can process $7.8 \times$ more graphs per second at a similar latency on average compared to a state-of-the-art model-specific FPGA accelerator targeting real-time applications on an AMD Ultrascale+ same-generation FPGA. It also achieves 5.8 $\times$ higher throughput compared to an Nvidia RTX A6000 GPU (8 nm) and $2.6 \times$ lower latency than a state-of-the-art accelerator that combines CPU-based graph preprocessing with AMD Versal (7 nm) fabric and AI engine compute. Finally, we present a case study for using our enhanced NPU in real-time GNNbased multi-input

关键词： Computational modeling Data preprocessing Full stack Computer architecture throughput Graph neural networks Real-time systems Software Vectors field programmable gate arrays

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Swarm Intelligence Algorithms and applications: An Experimental Survey 14th

Swarm Intelligence Algorithms and Applications: An Experimen...

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14th international conference on Swarm Intelligence (ICSI)

作者： Bari, Anasse Zhao, Robin Pothineni, Jahnavi Swetha Saravanan, Deepti NYU Courant Inst Math Sci Comp Sci Dept New York NY 10012 USA

ISBN: (纸本)9783031366215;9783031366222

Swarm Intelligence draws inspiration from the collective intelligent behavior of animals such as birds, fish, and bees. It refers to the collective behavior of decentralized, self-organized systems composed of many simple agents that interact with each other and their environment. As the Swarm Intelligence (SI) field expands, more SI meta-heuristics are incorporated into developing new Artificial Intelligence (AI) tools. this study presents a comprehensive survey of state-of-the-art Swarm Intelligence algorithms and their applications. Seven SI algorithms are described - Artificial Bee Colony Optimization, Bat-inspired algorithm, Flock by Leader algorithm, GreyWolf Optimizer, Flower Pollination Algorithm, WhaleOptimization, andMoth Flame Optimization, with their applications in three diverse fields: Scheduling Problem, Data Science and Robotics, and Route and Layout Optimization. the performance of the algorithms is compared experimentally, and discussions about future directions in Swarm Intelligence research are outlined.

关键词： Swarm Intelligence Artificial Intelligence Artificial bee colony optimization Whale Optimization Moth Flame Optimization Flower Pollination Algorithm Bat Algorithm Grey Wolf Optimization Bird Flocking Flock by Leader Swarm Intelligence applications

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