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检索条件"任意字段=14th International Conference on Field-Programmable Logic and Applications"

共 3172 条记录，以下是201-210 订阅

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Four-Valued Interpretation for Paraconsistent Annotated Evidential logic 14th

Four-Valued Interpretation for Paraconsistent Annotated Evid...

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14th international KES conference on Intelligent Decision Technologies, KES-IDT 2022

作者： Nakayama, Yotaro Akama, Seiki Abe, Jair Minoro Murai, Tetsuya Nihon Unisys Ltd. 1-1-1 Toyosu Koto-ku Tokyo135-8560 Japan C-Republic Inc. Kanagawa Asao-ku215-0012 Japan Graduate Program in Production Engineering Paulista University Rua Dr. Bacelar 1212 SP Sao Paulo04026-002 Brazil Chitose Institute of Science and Technology Hokkaido Chitose066-865 Japan

ISBN: (纸本)9789811934438

the paraconsistent annotated evidential logic E τ has been studied based on one of the applications of Paraconsistent Annotated logic. We propose an enhanced logical system T4E τ, an extended version of evidential annotated logics E τ, by adopting rough set theory for a semantic interpretation of truth-value and constructing another deductive system using tableau calculus adding some operations MAX and MIN. We also discuss the possibilities of applications of T4E τ to incorporate general decision logic. © 2022, the Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.

关键词： Rough set theory

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A Review on Elbow Biomechanics and Medical applications in the field of Biomedical Engineering 14

A Review on Elbow Biomechanics and Medical Applications in t...

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14th IEEE international conference on Humanoid, Nanotechnology, Information Technology, Communication and Control, Environment, and Management, HNICEM 2022

作者： Divierte, John Daniel A. Palabasan, Richard Cristian L. Ramos, Nialle Domzonn H. Rodelas, thaddeuz Jude R. Tan De Guzman, Gian Angelo L. Lavadia, William T. Vicerra, Ryan Rhay P. De la Salle University Department of Manufacturing Engineering and Management Manila Philippines

ISBN: (纸本)9781665464932

the study of elbow biomechanics and anatomy can be simplified into observing how the humerus articulates with the ulna and the radius to create a composite synovial hinge joint made up of three sliding joints movements like flexion, extension, pronation, and supination. through the humeroulnar, humeroradial, and radioulnar contact points, there exists cartilage, and various structures work together to stabilize and distribute the load on the joint. Knowledge of elbow biomechanics in conjunction with material selection allows biomedical engineers to understand better how to design prostheses that are biocompatible and ergonomic for the user. Total elbow arthroplasty is one example of an application of this topic in biomedical engineering. © 2022 IEEE.

关键词： Biomedical engineering

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FPGA-based Real-Time Spectral Peak Estimator for Radar Altimeter Signal Analysis

FPGA-based Real-Time Spectral Peak Estimator for Radar Altim...

引用

international conference on Communication Systems and Network Technologies (CSNT)

作者： Ritesh Kumar Sharma Jolly Dhar Umang Bhatia B Saravana Kumar Ch V N Rao D R Chowdhury Space Applications Centre Indian Space Research Organisation (ISRO) Ahmedabad India Department of Computer Science and Engineering Indian Institute of Technology (IIT) Kharagpur India

ISBN: (数字)9798331531935

ISBN: (纸本)9798331531942

this research work presents Real-Time Spectral Peak Estimator for radar altimeter signal analysis on an FPGA- based platform, focusing on accurate beat frequency estimation for precise above-ground level (AGL) altitude measurements. the proposed design is based on the first-order derivative difference estimator combined with zero crossover point detection to identify spectral maxima efficiently. this estimator is implemented using a fixed-point concurrent FPGA architecture to achieve high computational efficiency, low latency, and optimal hardware utilization, enabling real-time processing of radar return signals. this system has been verified and validated during various lab and field tests for the accurate beat frequency estimation under the dynamic signal conditions. the solution meets the stringent performance requirements of radar altimeter applications, making it suitable for aerospace, autonomous landing, and navigation systems where real-time accuracy is critical.

关键词： Accuracy Fast Fourier transforms Aerodynamics Real-time systems Frequency estimation Hardware Robustness Signal analysis Low latency communication field programmable gate arrays

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BitBlender: Scalable Bloom Filter Acceleration on FPGAs with Dynamic Scheduling

BitBlender: Scalable Bloom Filter Acceleration on FPGAs with...

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international conference on field programmable logic and applications

作者： Kenneth Liu Alec Lu Zhenman Fang HiAccel Lab Simon Fraser University Burnaby B.C Canada

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

the Bloom filter is one of the most widely used data structures in big data analytics to efficiently filter out vast amounts of noisy data. Unfortunately, prior Bloom filter designs only focus on single-input-stream acceleration, and can no longer match the increasing data rates offered by modern *** support large Bloom filters with low false-positive rate and high throughput, we present BitBlender, a configurable and scalable multi-input-stream Bloom filter acceleration framework in HLS. To effectively share one large bit-vector on chip among all streams, we design and implement the novel arbiter and unshuffle modules to dynamically schedule conflicting accesses to execute sequentially and non-conflicting accesses to execute in parallel. To support different user configurations of the Bloom filter, we also develop an automation flow, together with an accurate performance estimator, to automatically generate the best BitBlender design. Experimental results show that, on the AMD/Xilinx Alveo U280 FPGA, BitBlender achieves a throughput up to 2,194 MQueries/s (i.e., $8.8 \mathrm{~GB} / \mathrm{s}$) for a $\mathrm{9 6 M b}$ bit-vector with 0.01% false-positive rate. It achieves up to 10.4x speedup over a 24-thread CPU implementation and up to 4.9x speedup over a naively-duplicated multi-stream FPGA design. BitBlender will be released soon at https://***/SFU-HiAccel/BitBlender.

关键词： Matched filters Schedules Automation Prevention and mitigation System recovery throughput System-on-chip logic field programmable gate arrays Streams

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Decomposition Projective Method Based on Orthogonal Complement Space Combined with Finite Element Method and Its applications 14

Decomposition Projective Method Based on Orthogonal Compleme...

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14th international conference on Microwave and Millimeter Wave Technology (ICMMT)

作者： Wu, Yanfan Sun, Lianyou Hong, Wei Southeast Univ State Key Lab Millimeter Waves Nanjing 210096 Peoples R China

ISBN: (纸本)9781665467520

In order to solve the large-scale electromagnetic field problems with complex geometric structure. Combining Decomposition Projective Method(DPM) based on orthogonal complement space with finite element method(FEM) is presented firstly. Compared with the earlier DPM and the single FEM, this new method has many advantages that are very suitable for the above sort of problems. the reliability and effectiveness of this method are fully verified through the numerical examples.

关键词： Finite element method

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Pedestrian-Vehicle Interaction in Shared Space: Insights for Autonomous Vehicles 22

Pedestrian-Vehicle Interaction in Shared Space: Insights for...

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14th international ACM conference on Automotive User Interfaces and Interactive Vehicular applications (AutomotiveUI) - Diversity, Accessibility, Safety, and Human-Centered (D.A.S.H)

作者： Wang, Yiyuan Hespanhol, Luke Worrall, Stewart Tomitsch, Martin Univ Sydney Sydney Sch Architecture Design & Planning Design Lab Sydney NSW Australia Univ Sydney Australian Ctr Field Robot Sydney NSW Australia

ISBN: (纸本)9781450394154

Shared space reduces segregation between vehicles and pedestrians and encourages them to share roads without imposed traffic rules. the behaviour of road users (RUs) is then controlled by social norms, and interactions are more versatile than on traditional roads. Autonomous vehicles (AVs) will need to adapt to these norms to become socially acceptable RUs in shared spaces. However, to date, there is not much research into pedestrian-vehicle interaction in shared-space environments, and prior efforts have predominantly focused on traditional roads and crossing scenarios. We present a video observation investigating pedestrian reactions to a small, automation-capable vehicle driven manually in shared spaces based on a long-term naturalistic driving dataset. We report various pedestrian reactions (from movement adjustment to prosocial behaviour) and situations pertinent to shared spaces at this early stage. Insights drawn can serve as a foundation to support future AVs navigating shared spaces, especially those with a high pedestrian focus.

关键词： Pedestrian interaction Shared space Social norms Autonomous vehicles Human-machine interfaces

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HLS_Profiler: Non-Intrusive Profiling tool for HLS based applications 22

HLS_Profiler: Non-Intrusive Profiling tool for HLS based App...

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13th Annual ACM/SPEC international conference on Performance Engineering (ICPE)

作者： Sumeet, Nupur Deeksha Nambiar, Manoj Tata Consultancy Serv Res Mumbai Maharashtra India

ISBN: (纸本)9781450391597

the High-Level Synthesis (HLS) tools aid in simplified and faster design development without familiarity with Hardware Description Language (HDL) and Register Transfer logic (RTL) design flow that can be implemented on an FPGA (field programmable Gate Array). However, it is not straight forward to trace and link source code to synthesized hardware design. On the other hand, the traditional RTL-based design development flow provides the fine-grained performance profile through waveforms. With the same level of visibility in HLS designs, the designers can identify the performance-bottlenecks and obtain the target performance by iteratively fine-tuning the source code. Although, the HLS development tools provide the low-level waveforms, interpreting them in terms of source code variables is a challenging and tedious task. Addressing this gap, we propose to demonstrate an automated profiler tool, HLS_Profiler, that provides a performance profile of source code in a cycle-accurate manner.

关键词： Hardware profiling HLS Designs Performance Profile Performance Analysis

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Exploring FPGA designs for MX and beyond

Exploring FPGA designs for MX and beyond

引用

international conference on field programmable logic and applications

作者： Ebby Samson Naveen Mellempudi Wayne Luk George A. Constantinides Imperial College London London UK AMD Austin USA

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

A number of companies recently worked together to release the new Open Compute Project MX standard for low-precision computation, aimed at efficient neural network implementation. In this paper, we describe and evaluate the first open-source FPGA implementation of the arithmetic defined in the standard. Our designs fully support all the standard’s concrete formats for conversion into and out of MX formats and for the standard-defined arithmetic operations, as well as arbitrary fixed-point and floating-point formats. Certain elements of the standard are left as implementation-defined, and we present the first concrete FPGA-inspired choices for these elements, which we outline in the paper. Our library of optimized hardware components is available open source, and can be used to build larger systems. For this purpose, we also describe and release an open-source Pytorch library for quantization into the new standard, integrated with the Brevitas library so that the community can develop novel neural network designs quantized with MX formats in mind. We demonstrate the usability and efficacy of our libraries via the implementation of example neural networks such as ResNet-18 on the ImageNet ILSVRC12 dataset. Our testing shows that MX is very effective for formats such as INT5 or FP6 which are not natively supported on GPUs. this gives FPGAs an advantage as they have the flexibility to implement a custom datapath and take advantage of the smaller area footprints offered by these formats.

关键词： Training Quantization (signal) Accuracy Neural networks Libraries Usability Standards field programmable gate arrays Arithmetic Testing

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Revealing Untapped DSP Optimization Potentials for FPGA-Based Systolic Matrix Engines

Revealing Untapped DSP Optimization Potentials for FPGA-Base...

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international conference on field programmable logic and applications

作者： Jindong Li Tenglong Li Guobin Shen Dongcheng Zhao Qian Zhang Yi Zeng Brain-inspired Cognitive Intelligence Lab Institute of Automation Chinese Academy of Sciences Center for Long-term Artificial Intelligence School of Artificial Intelligence University of Chinese Academy of Sciences School of Future Technology Key Laboratory of Brain Cognition and Brain-inspired Intelligence Technology Chinese Academy of Sciences

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Systolic architectures are widely embraced by neural network accelerators for their superior performance in highly parallelized computation. the DSP48E2s serve as dedicated arithmetic blocks in Xilinx Ultrascale series FPGAs and constitute a fundamental component in FPGA-based systolic matrix engines. Harnessing the full potential of DSP48E2s in architectural design can result in significant performance enhancements for systolic architectures on Ultrascale series FPGAs. this paper unveils several previously untapped DSP optimization techniques capable of further enhancing FPGA-based systolic matrix engines. We apply these techniques to two well-known systolic architectures: Google TPUv1 and Xilinx Vitis AI DPU. With the proposed techniques, our design achieves substantial resource and power reduction compared to the open-source TPUv1 FPGA implementation and the Vitis AI DPU implementation in the same parallelism setting. We also demonstrate the applicability of our techniques to neuromorphic hardware for supporting spiking neural network acceleration.

关键词： Neuromorphics Prefetching Computer architecture Spiking neural networks Hardware Systolic arrays Artificial intelligence field programmable gate arrays Engines Optimization

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FlexiMem: Flexible Shared Virtual Memory for PCIe-attached FPGAs

FlexiMem: Flexible Shared Virtual Memory for PCIe-attached F...

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international conference on field programmable logic and applications

作者： Canberk Sönmez Mohamed Shahawy Cemalettin Cem Belentepe Paolo Ienne École Polytechnique Fédérale de Lausanne Lausanne Switzerland

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Shared Virtual Memory (SVM) is a mechanism that allows host-side applications and FPGA accelerators to access the same virtual address space. It enables accelerating algorithms with unpredictable memory access patterns by making transparent pointer sharing possible. Even for applications with predictable memory access patterns, SVM helps by eliminating manual data movement. FlexiMem is a customizable SVM system that uses FPGA-addressable memory resources to store virtual memory pages, rather than directly accessing the host memory, to achieve high throughput and low latency. On the FPGA side, FlexiMem features a highly-flexible interconnect that, for the first time, allows for configuring address and payload data paths independently for SVM systems. It supports multiple master and slave devices sharing the same address space, such as accelerators issuing many memory requests in parallel to multiple memory banks. With our interconnect design, we provide numerous specialization dimensions to optimize the SVM system for a given workload. For example, irregular applications with short accesses to memory require an address translation for each data transfer. Such applications can take advantage of a highly parallelized address data path and an increased number of TLBs working in parallel. In contrast, regular and bursting applications transfer a small number of address packets per many data packets, and they can tolerate a lightweight address data path with a single translation unit. FlexiMem also provides address translation units with reconfigurable capacities and page sizes to be tailored to the needs of the application. On the host side, FlexiMem leverages the Linux userfaultfd API and vendor-provided IPs and drivers for automatic data movement initiated by software. Blocks of memory allocated by the FlexiMem API can be passed freely to the FPGA or other host-side libraries, without requiring any kind of explicit data movement. We evaluate several experimental setups

关键词： Support vector machines Memory management Manuals throughput Prediction algorithms Software Main-secondary Low latency communication field programmable gate arrays Payloads

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