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检索条件"任意字段=14th International Conference on Field-Programmable Logic and Applications"

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Small Area Footprint FPGA Architecture for Approximate atan2(a, b) Algorithm 9

Small Area Footprint FPGA Architecture for Approximate atan2...

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9th IEEE Uttar Pradesh Section international conference on Electrical, Electronics and Computer Engineering, UPCON 2022

作者： Kumar, Bharat Sarawadekar, Kishor Dept. of Electronics Engineering Varanasi India

ISBN: (数字)9798350332506

ISBN: (纸本)9798350332506

Arctangent or inverse tangent function has numerous applications like gradient-based feature extraction, phase noise determination, range rate measurement etc. this paper presents a small area footprint hardware architecture for computing the arctangent of a complex number. the proposed method uses numerical approximation and LUTs used to improve the accuracy of the results obtained. Single-precision floating-point representation is used to implement the proposed design and the results demonstrate very good accuracy with an error of about ±0.0004 radian with 256×32 bits memory size. the proposed architecture is implemented on Nexys4 DDR FPGA board using Verilog and it operates at 19.8 MHz. Integrated logic Analyzer (ILA) is used to debug and validate the proposed design. Further, it is observed that results obtained with the proposed design are in agreement with the Matlab simulation results. © 2022 IEEE.

关键词： field programmable gate arrays (FPGA)

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14th international conference on Monte Carlo and Quasi-Monte Carlo Methods in Scientific Computing, MCQMC 2020

14th International Conference on Monte Carlo and Quasi-Monte...

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14th international conference on Monte Carlo and Quasi-Monte Carlo Methods in Scientific Computing, MCQMC 2020

ISBN: (纸本)9783030983185

the proceedings contain 15 papers presendted at a virtual meeting. the special focus in this conference is on Monte Carlo and Quasi-Monte Carlo Methods in Scientific Computing. the topics include: A Tool for Custom Construction of QMC and RQMC Point Sets;quasi-Monte Carlo Software;applications of Multivariate Quasi-Random Sampling with Neural Networks;a Note on Transformed Fourier Systems for the Approximation of Non-periodic Signals;scalable Control Variates for Monte Carlo Methods Via Stochastic Optimization;A fresh Take on ‘Barker Dynamics’ for MCMC;simulation of Conditional Expectations Under Fast Mean-Reverting Stochastic Volatility Models;density Estimation by Monte Carlo and Quasi-Monte Carlo;preface;on Dropping the First Sobol’ Point;generating From the Strauss Process Using Stitching;artificial Neural Networks Generated by Low Discrepancy Sequences;On the Selection of Random field Evaluation Points in the p-MLQMC Method.

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Artificial Intelligence in Music Education: Exploring applications, Benefits, and Challenges 14

Artificial Intelligence in Music Education: Exploring Applic...

引用

14th international conference on Educational and Information Technology, ICEIT 2025

作者： Yue, Yuanyang Jing, Yunqi School of Education Shanghai Normal University Tianhua College Shanghai China

ISBN: (纸本)9798331540883

this research investigates the present scenario of developments in artificial intelligence in music education in general and in various methods used to improve pedagogical practice as well as approaches that have developed in this field. the analysis is on benefits of integrating AI on teaching music on adapted learning experience, automated processes of assessments, and greater accessibility. It also takes into consideration challenges of integrating AI on teaching music on technological limitations, issues of ethics, and how teaching professionals can remain professional through continuing educations on ongoing bases. the conclusion is on offering ideas on how to carry out its research on its future along with real life implementation within this new body of literature. © 2025 IEEE.

关键词： Teaching

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LORA: A Latency-Oriented Recurrent Architecture for GPT Model on Multi-FPGA Platform with Communication Optimization

LORA: A Latency-Oriented Recurrent Architecture for GPT Mode...

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international conference on field programmable logic and applications

作者： ZhenDong Zheng Qianyu Cheng Teng Wang Lei Gong Xianglan Chen Cheng Tang Chao Wang Xuehai Zhou School of Computer Science and Technology Suzhou Institute for Advanced Research University of Science and Technology of China

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Large Language Models (LLMs) have been widely deployed in data centers to provide various services, among which the most representative is the Generative Pre-trained Transformer (GPT). the GPT model has heavy memory and computing overhead, and its inference process has two stages with distinct computing characteristics: Prefill and Decode. Utilizing existing GPUs and FPGA accelerators to construct a platform for deploying GPT in data centers faces the challenges of needing more effective synchronization schemes or structures with higher computational intensity. this paper proposes LORA, a low latency end-to-end GPT acceleration platform utilizing multiple FPGAs. Firstly, we optimize the synchronization timing of the GPT model to reduce the computation and communication overhead. Secondly, we devise some efficient synchronization steps for specific layers of the GPT model that overlap part of the computation and communication delay to improve the latency of our platform. Finally, we deploy recurrent structures on each FPGA to accelerate the different stages of the GPT model. Implemented on the Xilinx Alveo U280 FPGAs, LORA achieves an average $11.1 \times$ speedup over NVIDIA V100 GPUs on the modern GPT-2 model. Compared to the existing multi-FPGA accelerator appliance, LORA shows performance improvements of up to $4 \times$ and $2.7 \times$ in the Prefill and Decode stages.

关键词： Data centers Computational modeling LoRa Prototypes Transformers Data models Synchronization Low latency communication field programmable gate arrays Optimization

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NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions

NeuraLUT: Hiding Neural Network Density in Boolean Synthesiz...

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international conference on field programmable logic and applications

作者： Marta Andronic George A. Constantinides Department of Electrical and Electronic Engineering Imperial College London UK

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

field-programmable Gate Array (FPGA) accelerators have proven successful in handling latency- and resource-critical deep neural network (DNN) inference tasks. Among the most computationally intensive operations in a neural network (NN) is the dot product between the feature and weight vectors. thus, some previous FPGA acceleration works have proposed mapping neurons with quantized inputs and outputs directly to lookup tables (LUTs) for hardware implementation. In these works, the boundaries of the neurons coincide with the boundaries of the LUTs. We propose relaxing these boundaries and mapping entire sub-networks to a single LUT. As the sub-networks are absorbed within the LUT, the NN topology and precision within a partition do not affect the size of the lookup tables generated. therefore, we utilize fully connected layers with floating-point precision inside each partition, which benefit from being universal function approximators, but with rigid sparsity and quantization enforced between partitions, where the NN topology becomes exposed to the circuit topology. Although cheap to implement, this approach can lead to very deep NNs, and so to tackle challenges like vanishing gradients, we also introduce skip connections inside the partitions. the resulting methodology can be seen as training DNNs with a specific FPGA hardware-inspired sparsity pattern that allows them to be mapped to much shallower circuit-level networks, thereby significantly improving latency. We validate our proposed method on a known latency-critical task, jet substructure tagging, and on the classical computer vision task, digit classification using MNIST. Our approach allows for greater function expressivity within the LUTs compared to existing work, leading to up to $4.3 \times$ lower latency NNs for the same accuracy.

关键词： Training Quantization (signal) Neurons Artificial neural networks Tagging Vectors Table lookup Topology field programmable gate arrays Biological neural networks

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HASS: Hardware-Aware Sparsity Search for Dataflow DNN Accelerator

HASS: Hardware-Aware Sparsity Search for Dataflow DNN Accele...

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international conference on field programmable logic and applications

作者： Zhewen Yu Sudarshan Sreeram Krish Agrawal Junyi Wu Alexander Montgomerie-Corcoran Cheng Zhang Jianyi Cheng Christos-Savvas Bouganis Yiren Zhao Imperial College London UK University of Cambridge UK

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Deep Neural Networks (DNNs) excel in learning hierarchical representations from raw data, such as images, audio, and text. To compute these DNN models with high performance and energy efficiency, these models are usually deployed onto customized hardware accelerators. Among various accelerator designs, dataflow architecture has shown promising performance due to its layer-pipelined structure and its scalability in data *** weights and activations sparsity can further enhance memory storage and computation efficiency. However, existing approaches focus on exploiting sparsity in non-dataflow accelerators, which cannot be applied onto dataflow accelerators because of the large hardware design space introduced. As such, this could miss opportunities to find an optimal combination of sparsity features and hardware *** this paper, we propose a novel approach to exploit unstructured weights and activations sparsity for dataflow accelerators, using software and hardware co-optimization. We propose a Hardware-Aware Sparsity Search (HASS) to systematically determine an efficient sparsity solution for dataflow accelerators. Over a set of models, we achieve an efficiency improvement ranging from $1.3 \times$ to $4.2 \times$ compared to existing sparse designs, which are either non-dataflow or non-hardware-aware. Particularly, the throughput of MobileNetV3 can be optimized to 4895 images per second. HASS is open-source: https://***/Yu-Zhewen/HASS

关键词： Systematics Computational modeling Scalability Heuristic algorithms Memory management Artificial neural networks throughput Software logic Optimization

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Compact portable potentiostat for specific applications: development and measurements 14

Compact portable potentiostat for specific applications: dev...

引用

14th international conference on Advanced Semiconductor Devices and Microsystems, ASDAM 2022

作者： Szobolovszky, R. Donovalova, J. Powertec Ltd. Bratislava811 04 Slovakia

ISBN: (数字)9781665469791

ISBN: (纸本)9781665469777

thanks to constant progress, devices in the field of electrochemical analysis are more accurate and smaller in size. this enables the transfer of electrochemical analytical techniques outside the highly specialised laboratory to the commercial environment for direct application use. this trend creates a demand for portable, affordable devices, enabling user-intuitive testing even in the field. Considering these requirements, a potentiostatic platform was developed, enabling the use of various electrochemical analytical methods. the device contains a complete analog front end, a microcontroller controlled by supporting circuits and a communication interface. the device was tested and compared with reference laboratory potentiostats using standard solutions, thus demonstrating the accuracy of the developed platform. these experiments made it possible to qualitatively evaluate the platform's ability to perform cyclic voltammetry and differential pulse voltammetry. In addition, they demonstrated the ability of the device to work as a portable analytical potentiostat capable of measuring samples using basic electrochemical methods. © 2022 IEEE.

关键词： Cyclic voltammetry

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Leveraging HBM2 for Accelerating k-mer Counting with oneAPI on FPGAs

Leveraging HBM2 for Accelerating k-mer Counting with oneAPI ...

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international conference on field programmable logic and applications

作者： Owen P. Lucas Alan D. George NSF SHREC Center ECE University of Pittsburgh Pittsburgh USA

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Counting substrings of an arbitrary length k (k-mers) is the single most time-consuming step of de novo genome sequencing. Sequencing machines generate large quantities of data $(\gt100$ s of GBs per genome), which need to be processed using frequent memory accesses into data structures considerably larger than available cache, leading to a memorybound runtime. Stemming from the gap between processor and memory speed, this bottleneck requires alternative architectures. Recent FPGA devices, equipped with on-chip High-Bandwidth Memory (HBM), enable custom architectures to employ high-capacity, high-bandwidth memory to address memory-bound tasks. this research investigates accelerating k-mers counting with one such device, the BittWare 520N-MX, a Stratix 10 FPGA with 16 GB of on-chip HBM2. the architecture was designed using Intel’s oneAPI, which enables high-level synthesis for FPGA programming. the accelerator architecture was able to leverage inherent parallelism in the algorithm via the multiple parallel hash functions, along with partitioning data structure across multiple memory banks, and employing multiple independent parallel processing pipelines on the device to maximize throughput. the accelerator achieved $42.67 \mathrm{M} \boldsymbol{k}$-mers per second, $2.80 \times$ more than the throughput-optimized CPU version and $4.31 \times$ more than the original CPU app. Despite this speedup, the architectures saw diminishing returns when attempting to incorporate additional HBM2 banks. OneAPI was able to achieve speedup over the CPU using the FPGA and emerging memory, but it’s somewhat limited in its current scaling capabilities.

关键词： Performance evaluation Hash functions Sequential analysis Pipelines Parallel processing logic gates throughput System-on-chip Kernel field programmable gate arrays

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DTrans: A Dataflow-transformation FPGA Accelerator with Nonlinear-operators fusion aiming for the Generative Model

DTrans: A Dataflow-transformation FPGA Accelerator with Nonl...

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international conference on field programmable logic and applications

作者： Xuanzheng Wang Shuo Miao Peng Qu Youhui Zhang Department of Computer Science and Technology Beijing National Research Center for Information Science and Technology Tsinghua University

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

FPGA-based accelerators have emerged as an effective solution for GPT inference, given their inherent flexibility and capacity for domain-specific customization. However, the effective utilization of GPT has been hindered by two main obstacles: the unequal ratios between compute and memory access during the prefilling and generation stages, and the growing hardware resource requirements for nonlinear operations caused by longer text lengths and larger embedding dimensions. To address these challenges, we introduce DTrans, an FPGA accelerator specifically designed for GPT, which leverages nonlinear-operator fusion and a customized pipeline to efficiently handle long-input and long-generation tasks. We introduce a sequence-length-decoupled nonlinear operator design that enables in-place execution while preserving computational accuracy. Additionally, we employ a customized pipeline design that utilizes a two-level alternating input pipeline mapping for long-input tasks to alleviate the overhead associated with residual computation and on-chip buffers. Furthermore, for long-token generation tasks, our pipeline overlaps computational delays in operations such as Softmax and layer normalization with matrix operations. We also propose a novel two-stage dataflow transformation strategy that adopts different reuse strategies for the prefilling and generating stages with different computational/memory access characteristics. Our comparative analyses reveal that DTrans outperforms the GPU(V100) in terms of throughput and energy efficiency, achieving improvements of $11.99 \times$ and $11.7 \times$, respectively. When compared with state-of-the-art GPT inference accelerators, DTrans demonstrates more than $5.64 \times$ and $5.22 \times$ enhancements in these metrics.

关键词： Measurement Accuracy Pipelines Memory management throughput Energy efficiency System-on-chip Delays logic field programmable gate arrays

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High Sensitivity Integrated Optical Waveguide Electric field Sensor Based on Lithium Niobate 14

High Sensitivity Integrated Optical Waveguide Electric Field...

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14th international conference on Information Optics and Photonics, CIOP 2023

作者： Le, Qiu Yan, Song Bo, Peng Bao, Sun Shangjian, Zhang Zhiyao, Zhang Yong, Liu State Key Laboratory of Electronic Thin Films and Integrated Devices School of Optoelectronic Science and Engineering University of Electronic Science and Technology of China Chengdu610054 China School of Optoelectronic Science and Engineering University of Electronic Science and Technology of China Chengdu610054 China Beijing Institute of Radio Metrology and Measurement Beijing100854 China

ISBN: (纸本)9781510671744

Electric field sensing has wide applications in electromagnetic compatibility, communication, electromagnetic radiation, wireless monitoring in aviation, ***. With the development of precision devices, there is a growing need to measure weak electric field in complex environments. Traditional electric field sensors, due to the presence of multiple metal electrodes, often suffer from interference with the measured field, making it difficult to accurately measure weak electric field in space and unsuitable for narrow space field measurements due to their large size. In order to solve these problems, this paper presents a high-sensitivity electric field sensing chip based on lithium niobate material. the sensing chip adopts the Michelson interference for the sensing measurement of electric field. the sensor was designed for high sensitivity measurement at specific frequency. To demonstrate the versatility of the proposed solution, two target frequencies of 10 GHz and 12 GHz were designed to analyze the frequency response of various antenna parameters based on a tapered dipole antenna structure Based on the simulation. We fabricated electric field sensing chips with dimensions consistent with the simulation, parameters of dipole lengths 1.5 mm and 2 mm, and modulation electrode lengths of 4.4 mm and 5 mm were determined to fabricate the proposed chip. the fabricated chip size was 23.2mm × 4.6mm × 1.5mm. the experimental results demonstrated that the electric field sensing chips exhibited good linearity. Under the condition that the signal-to-noise ratio of 10dB, the measured sensitivities of the two sensing chips at their respective resonant frequencies were 41.6μV/m and 32.7μV/m. © 2023 SPIE.

关键词： Electric fields

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