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AgroLD: a Knowledge Graph for the Plant Sciences 14

AgroLD: a Knowledge Graph for the Plant Sciences

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14th international conference on Semantic Web applications and Tools for Health Care and Life Sciences, SWAT4HCLS 2023

作者： Larmande, Pierre Pitollat, Bertrand Tando, Ndomassi Pomie, Yann Happi, Bill Guignon, Valentin Ruiz, Manuel DIADE IRD Univ. Montpellier CIRAD Montpellier France -South Green Bioinformatics Platform Bioversity CIRAD INRAE IRD Montpellier France AGAP CIRAD INRAE Univ. Montpellier Montpellier France Bioversity International Montpellier France

Recent advances in high-throughput technologies have revolutionized the analysis in the field of the plant sciences. However, there is an urgent need to effectively integrate and assimilate complementary information to understand the biological system in its entirety. We have developed AgroLD, a knowledge graph that exploits Semantic Web technologies to integrate data of interest for the plant science community e.g., rice, wheat, arabidopsis and in this way facilitate the formulation and validation of new scientific hypotheses. AgroLD contains around 900M triples created by annotating and integrating more than 100 datasets coming from 15 data sources. Our objective is to offer a domain specific knowledge platform to answer complex biological and plant sciences questions related to the implication of genes in, for instance, plant disease resistance or adaptative responses to climate change. In this demo, we present some results which currently focused on genomics, genetics and trait associations. © 2023 Copyright for this paper by its authors. Use permitted under Creative Commons License Attribution 4.0 international (CC BY 4.0).

关键词： Knowledge graph

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A Low-profile Wideband Antenna for 5G Millimeter-Wave applications 14

A Low-profile Wideband Antenna for 5G Millimeter-Wave Applic...

引用

14th international conference on Microwave and Millimeter Wave Technology (ICMMT)

作者： Zhang, Zemin Yang, Guo-Min Fudan Univ Key Lab Elect Field & Elect Wave Shanghai 200433 Peoples R China

ISBN: (纸本)9781665467520

A low-profile wideband antenna put forward in this paper, which consists of one radiating patch and two symmetric parasitic patches. the antenna can be excited by microstrip lines through a novel U-slot-cut coupling aperture arrangement on the ground, which can enhance the impedance matching of the proposed antenna. Simulation consequences display an impedance bandwidth (vertical bar S-11 vertical bar <= - 10dB) of 25.4 GHz - 29.6 GHz (15%), significant improvement of operating bandwidth in a thickness only 0.03 lambda(0) (lambda(0) is wavelength of 28 GHz in free space). In this antenna, the peak-gain is more than 7 dBi at 28.5GHz. the proposed thin and wideband antennas show great potential in 5G millimeter wave (millimeter-wave) applications, especially thin electronic devices.

关键词： Slot antennas

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SA4: A Comprehensive Analysis and Optimization of Systolic Array Architecture for 4-bit Convolutions

SA4: A Comprehensive Analysis and Optimization of Systolic A...

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international conference on field programmable logic and applications

作者： Geng Yang Jie Lei Zhenman Fang Jiaqing Zhang Junrong Zhang Weiying Xie Yunsong Li Xidian University University of Technology Sydney Simon Fraser University

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Many studies have demonstrated that 4-bit precision quantization can maintain accuracy levels comparable to those of floating-point deep neural networks (DNNs). thus, it has sparked a keen interest in the efficient acceleration of such compressed DNNs, especially 4-bit convolutions, on edge devices. However, we observe that conventional systolic array (SA) architectures, widely adopted for DNN acceleration, fail to fully exploit the high computational density benefits of 4 -bit DSP packing. In this paper, we conduct the first comprehensive analysis of the integration of modern DSP packing techniques (specifically, 4-bit fully DSP packing) into the 4-bit systolic array design for convolutions. First, we introduce a row-temporal weight stationary 4-bit SA dataflow that complements the loop execution order inherent in 4-bit fully DSP packing in conventional SAs, which is called BaseSA. Next, we analyze the performance and resource efficiency of BaseSA, and identify two inefficiencies in the integration: 1) excessive LUT resource utilization that constraints the overall SA size, and 2) large latency gap to the theoretical optimum, due to various stalls in data supplies. To overcome these obstacles, we propose SA4: an HLS-based, customizable, and ultra-efficient hierarchical $\underline{\text { SA}}$ architecture optimized for 4 -bit convolutions. the core unit in SA4 is a delicately designed cost-effective SA unit (SAU), which 1) replaces the costly buffer-based data suppliers for activations and weights with shift-register-based ones, 2) replaces LUT-intensive FIFO connections between SA PEs (processing elements) with registers, and 3) replaces the finite state machines (FSM) and data unpacking logic inside each PE with a global FSM inside each SAU and a data splitter shared by a column of PEs. While such an SAU can only support a small spatial size for an SA due to its delicate design, we further scale it out using an array of SAUs. Experimental results show that our

关键词： Quantization (signal) Accuracy Computer architecture Artificial neural networks Systolic arrays Table lookup logic Resource management Optimization field programmable gate arrays

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Design of Restricted Coulomb Energy Neural Network Processor for Multi-modal Sensor Fusion 11th

Design of Restricted Coulomb Energy Neural Network Processor...

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11th international conference on Computer Science and its applications, CSA 2019 and 14th KIPS international conference on Ubiquitous Information Technologies and applications, CUTE 2019

作者： Cho, Jaechan Kim, Minwoo Jung, Yongchul Jung, Yunho School of Electronics and Information Engineering Korea Aerospace University Goyang-si Korea Republic of

ISBN: (纸本)9789811593420

this paper proposes a restricted coulomb energy neural network (RCE-NN) with an improved learning algorithm and presents the hardware architecture design and FPGA implementation results. the proposed learning algorithm divides each neuron region in the learning process and measures the reliability with different factors for each region. In addition, it applies a process of gradual radius reduction by a pre-defined reduction rate. In performance evaluations using two datasets, RCE-NN with the proposed learning algorithm showed high recognition accuracy with fewer neurons compared to existing RCE-NNs. the proposed RCE-NN processor was implemented in an Intel-Altera Cyclone IV FPGA with 26,702 logic elements, 13,096 registers and 131,072bits memory and operated at the clock frequency of 150 MHz. © 2021, Springer Nature Singapore Pte Ltd.

关键词： field programmable gate arrays (FPGA)

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A Large field-of-View Focal Plane Array based on Zernike Freeform Surface 14

A Large Field-of-View Focal Plane Array based on Zernike Fre...

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14th international conference on Microwave and Millimeter Wave Technology (ICMMT)

作者： Jiang, Zhe Qiu, Jinghui Harbin Inst Technol Sch Elect & informat Engn Harbin 150001 Peoples R China

ISBN: (纸本)9781665467520

applications of passive millimeter waves (PMMWs), especially PMMW imaging and PMMW radar, are required in medicine, homeland security, communication, and space technology, but constrained by the limited field-of-view (FoV) of focal plane array (FPA). In this paper, the influence of feed antenna tilt on antenna gain is investigated theoretically, and a forward free-form surface optimization method to expand FoV is proposed, thereby designing a wide-scan MMW focal plane array with a free-form surface reflector, which provides a high antenna gain of 46.5dB. the staggered placement of feed antennas achieves a 3dB effective isotropic radiated power (EIRP) within a relatively large field of view, up to +/-18.7 degrees. the FPA uses a paraboloid-based Zernike freeform reflector that optimizes the illumination of the far field region according to the feed pattern. In this way, we could improve the FoV and increase feed elements of the system without worrying about coupling efficiency between the focus field and single mode feed antenna.

关键词： Focal plane array (FPA) field-of-view (FoV) Zernike Free-form Surface

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An Optimization Method for Accelerating Convolutional Neural Networks Based on FPGA

An Optimization Method for Accelerating Convolutional Neural...

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Information and Communication Technology (ICTech), international conference of

作者： Dongji Li Zhenyu Yin Wei Gao MingZhi Hu Jianglin Du Liaoning Key Laboratory of Domestic Industrial Control Platform Technology on Basic Hardware & Software Shenyang University of Chemical Technology Shenyang China Liaoning Key Laboratory of Domestic Industrial Control Platform Technology on Basic Hardware & Software Shenyang Institute of Computing Technology Chinese Academy of Sciences Shenyang China Shenyang University of Chemical Technology Shenyang China

ISBN: (数字)9798350376258

ISBN: (纸本)9798350376265

Aiming at the problems of slow deployment of convolutional neural networks in the central processing unit (CPU) and high power consumption in the graphics processing unit (GPU), the convolutional neural network (CNN) developed based on the field programmable gate array (FPGA) platform is adopted. ) recognition system, which can achieve the effect of improving the operation speed of the algorithm. FPGA is a reconfigurable hardware device that can be programmed to implement various logic functions and can be optimized according to specific applications. through the design optimization of LeNet5, this paper designs a LeNet_Min network model with fewer parameters. Considering that the calculation amount of the algorithm and the consumption of logic resources are mainly concentrated in the convolution and pooling layers, a pipeline-based dual-channel data model is proposed. Comparison methods. In the pooling layer and activation function of convolutional neural network, flow pooling is designed, and the design method of activation function and pooling layer isomorphism is proposed. the test results show that the recognition speed of Letnet_Min is about 13 times that of the same network model realized by the CPU on the computer side, and higher than that of the GPU, and the system power consumption is only 1.96w. In addition, the system has high versatility and low resource occupation, and can be applied to other neural network models.

关键词： Multiplexing Power demand Computational modeling Graphics processing units programmable logic arrays logic gates Hardware Central Processing Unit Convolutional neural networks field programmable gate arrays

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Low Power Multiplier Using NAND logic Cells

Low Power Multiplier Using NAND Logic Cells

引用

international conference on Electronics, Materials Engineering and Nano-Technology (IEMENTech)

作者： A. K. tharun B. Chakradhar Reddy M. Vinodhini Department of Electronics and Communication Engineering Amrita School of Engineering Bengaluru Amrita Vishwa Vidyapeetham India

ISBN: (数字)9798331520762

ISBN: (纸本)9798331520779

Different models of multiplier that offer the least power consumption are designed as technology node changes. the motive of the designers is to work on the minimization of power with less penalty in speed and area. the main focus of the present development is on the low power multiplier design for the different applications. this paper proposes a method of an efficient Wallace Tree Multiplier which is power efficient and uses a 7:3 counter consisting of full adders implemented using the NAND logic cells. this proposed design is synthesized in the Cadence Genus tool which uses a 45 nm technology library cell in CMOS. the detailed comparison is performed between two multipliers in which one is designed using 2: 1 multiplexers and Exor gates that already exist and the other using NAND logic cells which is proposed for 4-bit operands. the proposed design of the multiplier which uses NAND logic cells shows that it takes less power and has less delay when it is compared to the multiplier which uses 2: 1 Multiplexers and Exor gates. this design gives a good performance for both FPGA and ASIC platforms.

关键词： Multiplexing Power demand logic gates Minimization Libraries Hardware Delays logic field programmable gate arrays Adders

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Artificial Neural Network Applied to Soccer field Reconstruction 14

Artificial Neural Network Applied to Soccer Field Reconstruc...

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14th IEEE international conference on Industry applications (INDUSCON)

作者： Lima, Felipe B. C. L. Doria, Fernando F. Real, Lucas Oliveira, Vinicius R. G. Takimoto, Rogerio Y. Sato, Andre K. Najafabadi, Hossein R. Tsuzuki, Fabio S. G. Tsuzuki, Marcos S. G. Escola Politecn Univ Sao Paulo Computat Geometry Lab Sao Paulo Brazil Media Portal Sao Paulo Brazil

ISBN: (纸本)9781665441186

the 3D reconstruction and automatic statistical analysis of sporting events is an area of increasing demand and innovation. In this work, it is proposed the use of two different CNNs (AlexNet and LeNet) with different activation functions for the classification of soccer field view. the images will be classified as viewing the right goal, the center field, and the left goal. the classification of the soccer field view facilitates the creation of an automated algorithm for creating correspondences of relevant points. this activity is the most difficult to be automated. As it is very difficult to obtain real images for training the CNNs, it is proposed a method for creating synthetic soccer field views. three CNNs presented good results and high accuracy.

关键词： Soccer games 3D reconstruction Soccer field detection Image processing Convolutional Neural Networks

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AMA: An Analytical Approach to Maximizing the Efficiency of Deep Learning on Versal AI Engine

AMA: An Analytical Approach to Maximizing the Efficiency of ...

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international conference on field programmable logic and applications

作者： Xiaodong Deng Shijie Wang Tianyi Gao Jing Liu Longjun Liu Nanning Zheng National Key Laboratory of HumanMachine Hybrid Augmented Intelligence National Engineering Research Center for Visual Information and Applications and Institute of Artificial Intelligence and Robotics Xi’an Jiaotong University

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

the traditional cache-based multi-core architecture represented by CUDA has been plagued by the “memory wall” problem, and a large number of applications represented by large language model inference are unable to meet the high computational intensity requirements. the Versal AI Engine architecture provides a variety of rich inter-core connections in the processor array, increasing many data reuse opportunities and potentially alleviating the “memory wall” issue. However, traditional parallel programming models cannot be directly applied to this architecture, and how to map computations to achieve high computational utilization becomes a new challenge. To address this, we propose AMA, a hierarchical performance analysis model built on the Versal AI Engine architecture, designed to maximize the efficiency of typical deep learning applications. Experiments show that AMA modeling is accurate and efficient. On the VCK190 platform, we achieved a matrix multiplication throughput of 5867.29 GFLOPS in fp32 and 88.55 TOPS in int8, and a convolution throughput of 99.6770 TOPS. In terms of energy efficiency, AMA achieved 142.68 GFLOPS/W in fp32 precision and 1.416 TOPS/W in int8 matrix multiplication. Compared to the current state-of-the-art methods, we achieved a $\mathbf{1 4. 9 9 \%}$ increase in throughput and a 22.92% increase in energy efficiency, providing new analytical performance model and practical guidance for efficient deep learning deployment on AI Engine.

关键词： Deep learning Analytical models Convolution Computational modeling Computer architecture throughput Energy efficiency Performance analysis Computational efficiency Engines

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Power Quality Improvement using a Robust Voltage Vector-Controlled three-Phase SAPF-based Fuzzy logic and Space Vector Modulation

Power Quality Improvement using a Robust Voltage Vector-Cont...

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international conference on Intelligent Systems: theories and applications (SITA)

作者： Bouchaib Essoussi Ahmed Moutabir Bahloul Bensassi Abderrahmane Ouchatti Yassine Zahraoui Bouchaib Benazza Electrical Engineering Department Hassan II University FSAC Casablanca Morocco Electrical Engineering Department Hassan II University ENSAM-C Casablanca Morocco Electrical Engineering Department Mohammed V University ENSAM-R Rabat Morocco

the multiplication of nonlinear loads leads to significant degradation of the energy quality. thus the interconnection network is subject to being polluted by the generation of harmonic components and reactive power, which causes a weakening efficiency, especially for the power factor. this research treats the modeling of robust voltage-oriented control (VOC) for a shunt active power filter (SAPF). To sustain the DC-bus voltage, a fuzzy logic controller (FLC) based Mamdani algorithm is synthesized to ensure active power control. Besides, a robust PLL-based bandpass multivariate filter (BPMVF) is used to ameliorate the network voltage quality. Furthermore, a space vector modulation (SVM) is inserted. A unitary power factor and sinusoidal network current are supplied with no requirement for a PWM generator, and with fewer harmonics. Expanded simulation results obtained from the transient and steady-state have demonstrated high performance and have verified the effectiveness of the suggested power control.

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