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Trends and applications of Robotics Development in Virtual Environments

Trends and Applications of Robotics Development in Virtual E...

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international conference on Information and Communication Technology Convergence (ICTC)

作者： Joon Young Kim Jeong Min Oh School of AI Convergence Sungshin Women’s University Seoul South Korea

In this paper, we investigated the current trends and applications of robotics development in virtual environments since robotics has become the main in the mobility service field. First, we identified the various components of robotic systems in which components can be used and developed in virtual spaces. After our analysis, we followed up on the current technical robot trends by running four simulators to verify development capabilities. In addition, we discussed the possible considerations and issues associated with robotics development in virtual settings.

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Better Together: Combining Analytical and Annealing Methods for FPGA Placement

Better Together: Combining Analytical and Annealing Methods ...

引用

international conference on field programmable logic and applications

作者： Rachel Selina Rajarathnam Kate thurmer Vaughn Betz Mahesh A. Iyer David Z. Pan Dept. of Electrical and Computer Engineering The University of Texas at Austin Austin TX USA Dept. of Electrical and Computer Engineering University of Toronto Toronto ON Canada Intel Corporation San Jose CA USA

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Placement is a critical step in the FPGA design implementation flow that strongly impacts routability and timing closure. Recent state-of-the-art academic analytical placers have achieved impressive scalability but are limited to AMD Ultrascale-like architectures and mostly synthetic designs. On the other hand, VPR, the place and route tool within the widely used open-source Verilog-to-Routing (VTR) toolchain, can produce a legal placement for any arbitrary architecture; however, its simulated annealing placer scales poorly. thus, there is a clear need to bring scalable, high-quality placement to realistic architectures and circuits. In this work, we develop a hybrid framework that combines the strength of a scalable flat analytical placer with the flexibility of simulated annealing techniques to adapt to various architectures and circuits, substantially improving the quality of results. We augment the state-of-theart analytical elfPlace FPGA placer as aug-elfPlace, generalizing its architecture modeling to handle real-world constraints and target different and more complete architectures. We leverage VPR’s legalization capability to integrate with external placers such as aug-elfPlace. VPR’s simulated annealing placer can further optimize the legalized placement, and VPR’s router and timing analysis can provide final quality results. By integrating wirelength-driven aug-elfPlace and VPR, our hybrid framework achieves up to 2% timing improvement with 15% reduction in routed wirelength compared to timing-driven VPR, on average across the large and heterogeneous Titan23 benchmark suite targeting an Intel Stratix-IV-like architecture.

关键词： Measurement Analytical models Annealing Scalability Circuits Simulated annealing Benchmark testing Routing field programmable gate arrays Video recording

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Design and Implementation of an Efficient Quantum Cost Optimized Adder Using Reversible logic Gates

Design and Implementation of an Efficient Quantum Cost Optim...

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international conference on Electronics, Materials Engineering and Nano-Technology (IEMENTech)

作者： Shatavisha Dasgupta Sourav Pandey Debjit Roy Agnik Maity Antarik Sinha Mihir Lal Saha dept. of Electronics and Communication Engineering Institute of Engineering & Management Under Univeristy of Engineering & Management kolkata Kolkata India

ISBN: (数字)9798331520762

ISBN: (纸本)9798331520779

In modern Very-Large-Scale Integration (VLSI) technology, managing information loss is a critical challenge. Conventional logic gates, such as AND, OR, and NOT, are prone to data loss during operations, reducing their efficiency for sophisticated applications. Reversible logic gates, which have an equal number of inputs and outputs, offer a solution by preserving data integrity. this paper presents the design and FPGA implementation of an efficient and high-speed full adder circuit utilizing reversible logic gates, namely Feynman, Toffoli, and Peres gates. the design focuses on improving computational efficiency and thermal performance. An analysis of the circuit's quantum cost, garbage outputs, and ancillary inputs reveals its advantages over traditional designs. Proposed design has been realized using Verilog and Synthesize and simulations performed using Xilinx Vivado and Xilinx ISE tools, confirms the functionality and efficiency of the proposed full adder. FPGA implementation of the design has been done using NEXYS A7 (Artix 7 series). the results show that the circuit has a quantum cost of 10, with two garbage outputs and one ancillary input, underscoring its potential for use in low-power, high-performance computing systems and quantum computing applications.

关键词： Performance evaluation Costs Quantum computing Simulation logic gates Very large scale integration thermal management Hardware design languages Adders field programmable gate arrays

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Attention-Based Scene Graph Generation: A Review 14

Attention-Based Scene Graph Generation: A Review

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14th international conference on Software, Knowledge, Information Management and applications, SKIMA 2022

作者： Airin, Afsana Dawla, Rezab Ud Noor, Ahmed Shabab Al Hasan, Muhib Hasan, Ahmed Rafi Zaman, Akib Farid, Dewan Md. United International University Department of Computer Science & Engineering Badda Dhaka1212 Bangladesh

ISBN: (纸本)9781665493345

the automated creation of a semantic structural scene graph from an image or video is known as scene graph generation (SGG), which includes accurate labeling of all objects that are identified and the interconnections between them. Several SGG methods have been proposed employing deep learning techniques nowadays to achieve good results but most of the approaches failed to integrate the contextual information of pair of objects. Apart from the existing state of the arts of SGG, the attention mechanism is creating a new horizon in this field. this paper offers a thorough analysis of the most recent Attention-Based Scene Graph Generation techniques. In this paper, we have compared and tested five existing Attention-Based Scene Graph Generation methods. We have summarised the results of existing methods to understand progress in this field of Scene Graph Generation. Moreover, we have discussed the strengths of existing techniques and future directions of attention-based models in Scene Graph Generation. © 2022 IEEE.

关键词： Semantics

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Realization of CNN Using Hybrid Multiplier With PYNQ-Z2

Realization of CNN Using Hybrid Multiplier With PYNQ-Z2

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international conference on Computing and Networking Technology (ICCNT)

作者： A. Umamaheswari S. Kripa V. Jeyalakshmi Department of ECE CEG Anna University Chennai India

ISBN: (数字)9798350370249

ISBN: (纸本)9798350370270

Smart technologies namely Machine Learning (ML) and Deep Learning (DL) are evolved day by day to develop smart products for various applications. Deep learning is one of the recent technology, which is widely applicable for all kind of applications. CNN (Convolutional Neural Network) is the basic structure to simulate the deep learning algorithms. So various structure of CNN is studied and the selected structure is used for classification of images. then the selected CNN structure is further analyzed for its performance in the FPGA (field programmable Gate Array) board. LeNet and EfficientNet uses MNIST and CIFAR-10 datasets to analyse the performance in both software and hardware. By comparing the performance of EfficientNet, it takes 124 ms in software and 0.172 ms in hardware to classify a single image. Whereas LeNet takes 19 ms and 0.16 ms in software and hardware respectively. CNN performance can be highly improved by exploring the hardware resources of the FPGA chip. An efficient multiplier is designed here for LeNet to reduce the utilization of hardware resources. By implementing it, the area utilized is reduced by $51.2 \%$ than by using conventional multiplier for CNN.

关键词： Deep learning Runtime Machine learning algorithms logic gates Hardware Software Real-time systems Classification algorithms Convolutional neural networks field programmable gate arrays

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A Reactive System-Specific Compilation Chain from Synchronous Dataflow Models to FPGA Netlist

A Reactive System-Specific Compilation Chain from Synchronou...

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IEEE international conference on Space Mission Challenges for Information Technology, SMC-IT

作者： Inès Winandy Arnaud Dion Pierre-Loïc Garoche Florent Manni Fédération ENAC ISAE-SUPAERO ONERA Université de Toulouse Toulouse France CNES - Centre national d'études spatiales Toulouse France

ISBN: (数字)9798350384512

ISBN: (纸本)9798350384529

Modern field programmable Gate Arrays (FPGAs) offer a solution to several issues related to real-time on-board systems, such as guaranteed execution time. they are currently considered as target platforms for space applications. How-ever, the complexity of producing circuits on these components poses a challenge to their widespread adoption. To address this issue, high-level synthesis tools provide another layer of abstraction above the logic circuit design process, for example compiling C code into Hardware Description Languages such as VHDL or Verilog. However, high-level synthesis results are poorly predictable and do not guarantee the efficient use of recent FPGA capabilities provided by new primitives like digital signal processor or random-access memory. In this paper we propose a compilation chain dedicated to reactive systems, ie. controllers, providing a more predictable synthesis process for critical embedded control applications. the implemented solution demonstrates timing performance equivalent to the traditional synthesis process with a more predictable result.

关键词： Solid modeling Analytical models VHDL Space missions Circuits Hardware Timing Numerical models Integrated circuit modeling field programmable gate arrays

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Design of High-Speed Multipliers using Counter based 4:2 Compressor with Pre-Processing

Design of High-Speed Multipliers using Counter based 4:2 Com...

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international conference on Information Technology and Electrical Engineering (ICITEE)

作者： Pavitra Y J Mahanta Talakal Department of Electronics and Communication Engineering PES University Bangalore India

ISBN: (数字)9798350375817

ISBN: (纸本)9798350375824

Adders and multipliers form the basic building blocks in most of the system designs. Multipliers are widely used in arithmetic and logic units, digital signal processing, audio processing, and image processing applications. Multipliers have complex structures and optimization of multiplier designs plays a vital role in improving the performance parameters like area, power, and delay. the proposed work aims to design compressor-based multipliers using counter logic for power and delay-efficient models. A novel 4:2 counter-based compressor with pre-processing is proposed to design multipliers to improve performance parameters like area power and delay. the proposed designs are synthesized on Cadence Genus with 90nm technology. Experiments carried out reveal that the proposed multipliers save a maximum of 21.71% of area, and 75.63% of power and improve speed by 24.28% over multipliers reported in the literature.

关键词： Electrical engineering Image coding Digital signal processing Delays logic Information technology System analysis and design Optimization field programmable gate arrays Arithmetic

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A Dataflow Overlay for Monte Carlo Multi-Asset Option Pricing on AMD Versal AI Engines

A Dataflow Overlay for Monte Carlo Multi-Asset Option Pricin...

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ISC High Performance 2025 Research Paper Proceedings (40th international conference)

作者： Mohamed Bouaziz Michael Samet Suhaib A. Fahmy KAUST Thuwal Saudi Arabia RWTH Aachen University Aachen Germany

ISBN: (数字)9783982633619

Monte Carlo simulations are widely used for financial applications, particularly in option pricing. Multi-asset option pricing has not been as widely investigated as single-asset problems and presents specific challenges. this paper presents an efficient way to design a dataflow overlay for multi-asset option pricing on AMD Versal AI Engines by leveraging their SIMD capabilities and the high-performance interconnect network linking them. the proposed dataflow overlay achieves a highly scalable parallelized implementation that can utilize nearly the totality of the available AI Engines on the AMD Versal VCK5000 accelerator. We also show that it achieves up to 25.7× speedup over a traditional FPGA programmable logic implementation using the Vitis Quantitive Finance Library, a specialized AMD library for quantitative finance on FPGAs, and up to 13.41× speedup over a highly parallelized CPU implementation over 128 threads. We show that although an Nvidia RTX A6000 GPU implementation has 0.73× the execution time of our design, our design achieves 1.82× the energy efficiency.

关键词： Pricing Engines Computational modeling Finance Artificial intelligence field programmable gate arrays Stochastic processes Mathematical models Computer architecture Accuracy

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A Wideband SIW-Fed Cavity-Backed Antenna for W-Band applications 14

A Wideband SIW-Fed Cavity-Backed Antenna for W-Band Applicat...

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14th international conference on Microwave and Millimeter Wave Technology (ICMMT)

作者： Zhang, Jinping Yang, Guopeng Ma, Tianye Jiang, Wen Nanjing Res Inst Elect Technol Natl Key Lab Antenna & Microwave Technol Nanjing Peoples R China

ISBN: (纸本)9781665467520

A substrate-integrated-waveguide(SIW) fed cavity-backed antenna based on multilayer quartz-glass substrates is discussed in this paper. In order to obtain a large bandwidth, the antenna is composed of three layers of substrate, the field radiation is carried out through a cavity surrounded by the through-glass-vias(TGVs), and the SIW structure is used for feeding. Simulation results show that the VSWR<2 bandwidth of the antenna ranges from 67 to 110GHz, and its size is only about half of the wavelength corresponding to 100GHz. the radiation characteristics are also good. the 3-dB beamwidths of E-plane and H-plane are both greater than 80 degrees at 110GHz and the pattern changes slowly in the operating band. these good performances indicate that the antenna can be well integrated with the RFIC through SIW structure and can well meet the requirements of millimeter wave array applications.

关键词： Substrate integrated waveguides

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A Low-profile Broadband Array Antenna with Elliptical Radiating Elements for Millimeter-Wave applications 14

A Low-profile Broadband Array Antenna with Elliptical Radiat...

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14th international conference on Microwave and Millimeter Wave Technology (ICMMT)

作者： Liu, Pengfei Zhou, Yaru Sun, Jinlong Gui, Guan Nanjing Univ Posts & Telecommun Nanjing Peoples R China State Key Lab Millimeter Waves Nanjing Peoples R China

ISBN: (纸本)9781665467520

A low-profile broadband array antenna, which is designed for millimeter-wave (mmW) communications, is proposed in this paper. A one-to-eight way power divider excites the array antenna, which adopts substrate integrated waveguide (SIW) transmission line. the array elements are eight dual-elliptical models. A coupling slot on the SIW is etched to feed the radiators. Simulated results claim that the proposed array antenna achieves an S-11 < -10 dB bandwidth of 32.5 35.0 GHz and a gain of 15.7 dBi at 34GHz. In addition to the far-field radiation characteristics and convenient processing, the array antenna is especially suitable for applications of mmW communications.

关键词： low-profile array antenna millimeter-wave (mm ll) substrate integrated waveguide (Sill) dual-elliptical model

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