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检索条件"任意字段=14th International Conference on Field-Programmable Logic and Applications"

共 3172 条记录，以下是291-300 订阅

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New Design of Efficient Reversible Quantum Saturation Adder

New Design of Efficient Reversible Quantum Saturation Adder

引用

international econference on Computer and Knowledge Engineering (ICCKE)

作者： Negin Mashayekhi Mohammad Reza Reshadinezhad Shekoofeh Moghimi Faculty of Computer Engineering University of Isfahan Isfahan Iran

ISBN: (数字)9798331511272

ISBN: (纸本)9798331511289

Reversible logic is becoming increasingly important with the rise of technologies like quantum computing, as it retains information during computation and maintains a one-to-one mapping between input and output patterns. Quantum circuits are inherently reversible and the best computational model in quantum computing systems. Some quantum signal processing applications like filters and image processing applications require the results of arithmetic operations to be saturated. Saturation occurs when adding two numbers with the same sign and this can be done through a quantum saturating adder. this paper proposed a reversible quantum saturating adder with efficient quantum criteria like quantum cost, number of ancilla, and number of garbage outputs. We firstly propose a reversible n-bit quantum saturation generator block which is applied to a quantum adder and construct a quantum saturating adder circuit. the proposed circuit is simulated using the Quirk online tool and the result confirms the accuracy of the design. this design achieves 18% and 33% improvement in quantum cost and garbage outputs, compared to its counterpart, respectively.

关键词： Measurement Costs Power demand Image processing Quantum state logic gates Generators logic Quantum circuit Adders

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High-Speed Chromatic Dispersion Compensation Filtering in FPGAs for Coherent Optical Communication 30

High-Speed Chromatic Dispersion Compensation Filtering in FP...

引用

30th international conference on field-programmable logic and applications (FPL)

作者： Bae, Cheolyong Gustafsson, Oscar Linkoping Univ Dept Elect Engn Linkoping Sweden

ISBN: (纸本)9781728199023

Chromatic dispersion is one of the error sources limiting the transmission capacity in coherent optical communication that can be mitigated with digital signal processing. In this paper, the current status and plans of implementation of chromatic dispersion compensation (CDC) filters on FPGAs are discussed. As these high-speed filters are most efficiently implemented in the frequency-domain, different approaches for high-speed FFT-based architectures are considered and preliminary results of fully parallel FFT implementation by utilizing FPGA hardware features are presented.

关键词： Chromatic dispersion compensation (CDC) fast Fourier transform (FFT) field-programmable gate arrays (FPGAs)

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Hardware Implementation of the Precision Time Base Technique for Digital Sampling Oscilloscopes on FPGA

Hardware Implementation of the Precision Time Base Technique...

引用

Digital Signal Processing and its applications (DSPA), international conference on

作者： Bilal Moussa Kabalan Chaccour Rachid Bouyekhf Multilane Inc. Research and Development Department Houmal Technology Park Bdadoun Lebanon Dept. of Computer and Communications Engineering TICKET Lab. Antonine University Hadat-Baabda Lebanon Nanomedicine Imagery and Therapeutics (NIT) Lab. UTBM Belfort cedex France

In this paper we investigate implementing a Precision Time Base (PTB) technique to improve measurement jitter performance of digital sampling oscilloscopes (DSO) on a field programmable Gate Array (FPGA). To achieve better measurements, two reference signals are used to correct time-base errors and minimize jitter added by the DSO itself (minimize measurement jitter). We show experimentally that using the aforementioned technique, measurement jitter can be reduced from 1.3 pico-seconds (ps) to 280 femto-seconds (fs) (depending on the data rate and the pattern length) on a high-speed DSO.

关键词： Power demand Measurement uncertainty Oscilloscopes Jitter Parallel processing logic gates Length measurement

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Characterizing Latency Overheads in the Deployment of FPGA Accelerators 30

Characterizing Latency Overheads in the Deployment of FPGA A...

引用

30th international conference on field-programmable logic and applications (FPL)

作者： Cooke, Ryan A. Fahmy, Suhaib A. Univ Warwick Sch Engn Coventry W Midlands England

ISBN: (纸本)9781728199023

FPGA hardware accelerators have recently enjoyed significant attention as platforms for further accelerating computation in the datacenter but they potentially add additional layers of hardware and software interfacing that can further increase communication latency. In this paper, we characterize these overheads for streaming applications where latency can be an important consideration. We examine the latency and throughput characteristics of traditional server-based PCIe connected accelerators, and the more recent approach of network attached FPGA accelerators. We additionally quantify the additional overhead introduced by virtualising accelerators on FPGAs.

关键词： field programmable gate arrays (FPGA)

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Fuzzy logic-Based AI Model for Accurate Grading of Papilledema Severity

Fuzzy Logic-Based AI Model for Accurate Grading of Papillede...

引用

Electrical Engineering (ICEENG), 12th international conference on

作者： Ahmed M. Salaheldin Manal Abdel Wahed Manar Talaat Neven Saleh Biomedical Engineering Department Higher Institute of Engineering EL Shorouk Academy Cairo Egypt Biomedical Engineering Department Faculty of Engineering Cairo University Giza Egypt Department of ophthalmology Faculty of Medicine South Valley University Qena Egypt

ISBN: (数字)9798350343427

ISBN: (纸本)9798350343434

Papilledema is characterized by optic disc swelling due to increased intracranial pressure, necessitates accurate diagnostic tools for effective treatment planning. this study presents an innovative artificial intelligence (AI) model employing fuzzy logic to grade papilledema severity. the study utilized a newly collected dataset containing different clinical measurements. the input of the system includes Best-Corrected Visual Acuity (BCVA), pupil reaction, retinal nerve fiber layer (RFNL) thickness, total peripapillary thickness, and visual field measurements and output of the system is to identify the level of severity of papilledema within four grades. the fuzzy logic model achieves a classification accuracy exceeding 90%, demonstrating its effectiveness in discerning diverse papilledema severity levels. Comparative analysis with existing literature highlights competitive performance, positioning the model as a promising neuro-ophthalmological diagnostic tool. Unique contributions include dataset composition, feature extraction, and the model's implementation. this study pioneers in advancing diagnostic methodologies for papilledema, offering a reliable tool for ophthalmologists used for the first time in papilledema severity detection. the results indicate the model's potential for integration into clinical practice, contributing AI-driven neuro-ophthalmological diagnostics and enhancing patient care.

关键词： Fuzzy logic Optical fibers Visualization Accuracy Retina Robustness Planning

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FPGA based Optimized Decimator using Distributed Arithmetic Algorithm for Wireless applications 6

FPGA based Optimized Decimator using Distributed Arithmetic ...

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6th international conference for Convergence in Technology (I2CT)

作者： Singh, Lajwanti Geetanjali Mehra, Rajesh Banasthali Vidyapeeth Univ Vanasthali Rajasthan India NITTTR ECE Dept Chandigarh India

ISBN: (纸本)9781728188768

In this paper, FPGA based enhanced decimator utilizing DA is introduced for remote applications for giving better answers for inspecting rate modifications. the proposed decimator is planned utilizing Poly stage disintegration strategy. Circulated Arithmetic (DA) Algorithm which is a multiplier free methodology is utilized for devouring less equipment assets and to bring about a rapid decimator. Equipment multifaceted nature is decreased by utilizing advanced Look up Table (LUT) apportioning. the proposed configuration shows an improvement of 6.2-14% in speed. By devouring practically same number of cuts and F/Flops, number of LUTs is diminished by 11.95-17.63% demonstrating prudent arrangement. At long last the created decimator configuration is mimicked and incorporated on Virtex 2 Pro based objective field programmable Gate Array (FPGA).

关键词： Distributed Arithmetic loritIun field programmable Gale Array Decimator Sub band Coding Look up Table

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TTA-SIMD Soft Core Processors 30

TTA-SIMD Soft Core Processors

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30th international conference on field-programmable logic and applications (FPL)

作者： Tervo, Kati Malik, Samawat Leppanen, Topi Jaaskelainen, Pekka Tampere Univ Tampere Finland

ISBN: (纸本)9781728199023

Soft processors are an important tool in the field programmable Gate Array (FPGA) designer's toolkit, and their Single Instruction Multiple Data (SIMD) organizations are an efficient means to utilize the parallelism of FPGAs. However, the state-of-the-art SIMD processors are hindered by the additional logic complexity resulting from dynamic features. By minimizing such constructs, it is possible to design soft processors that are efficient but still flexible enough to operate within an application domain. To this end, we propose a family of instruction set programmable multi-issue wide SIMD soft cores. the template is based on a highly static Transport Triggered Architecture (TTA) and a design time customizable shuffle unit to minimize inefficient dynamic features while remaining compiler programmable. the cores are evaluated on the PYNQ-Z1 board against the ARM A9 hard processor system with NEON vector extensions. the proposed cores reach up to 2.4x performance improvement over the ARM, can fit up to 1024 bit wide SIMD units onto the relatively small FPGA, while still operating at above 100 MHz. the scalability of TTA enables state of the art vector widths. the multicore scalability of the template is preliminarily tested with a 14-core design on a XCZU9EG FPGA customized for real-time convolutional neural net inference.

关键词： field-programmable Gate Array (FPGA) Transport-Triggered Architecture (TTA) Single Instruction Multiple Data (SIMD)

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Incorrectness logic for Graph Programs 14th

Incorrectness Logic for Graph Programs

引用

14th international conference on Graph Transformation (ICGT) Held as Part of conference on Software Technologies - applications and Foundations (STAF)

作者： Poskitt, Christopher M. Singapore Management Univ Singapore Singapore

ISBN: (纸本)9783030789466;9783030789459

Program logics typically reason about an over-approximation of program behaviour to prove the absence of bugs. Recently, program logics have been proposed that instead prove the presence of bugs by means of under-approximate reasoning, which has the promise of better scalability. In this paper, we present an under-approximate program logic for a nondeterministic graph programming language, and show how it can be used to reason deductively about program incorrectness, whether defined by the presence of forbidden graph structure or by finitely failing executions. We prove this 'incorrectness logic' to be sound and complete, and speculate on some possible future applications of it.

关键词： Program logics Under-approximate reasoning Bugs

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An Enhanced DSP Block Architecture for FPGA Supporting Multi-operands Addition Operation 14

An Enhanced DSP Block Architecture for FPGA Supporting Multi...

引用

14th IEEE international conference on ASIC, ASICON 2021

作者： Chen, Sanlin Cai, Gang Huang, Zhihong Chinese Academy of Sciences Aerospace Information Research Institute Beijing100094 China

ISBN: (纸本)9781665411493

the DSP block can effectively improve the performance of arithmetic operation in FPGA. However, the commercial FPGA does not directly support multi-operands addition operation which is used in multiple application scenarios such as FIR. Using traditional DSP block to realize multi-operands addition operation will take up a lot of logic resources and affect the performance. In this paper, three Multiplier or Addition Blocks (MABs) are proposed, which enable the DSP block to directly support multi-operands addition operation with high performance. Besides, an index to measure the area utilization rate of DSP block performing addition operation is proposed. Compared with the traditional method, the design proposed in this research can realize multi-operands addition operation by only using DSP block without occupying other logical resources in FPGA. Based on Stratix-IV DSP block architecture, this experiment replaces multiplier with the MABs proposed in this paper. We use SMIC 40nm standard CMOS process to design and complete the implementation of the overall circuit. the experimental results show that the proposed design can realize two sets of eight 18-bit signed number addition operation at the cost of additional 7.48% area without affecting the existing functions of DSP block and the performance can reach 500MHz. © 2021 IEEE.

关键词： field programmable gate arrays (FPGA)

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High Performance Mixed logic Decoders using MOS like GNRFET in 22nm Technology 4

High Performance Mixed Logic Decoders using MOS like GNRFET ...

引用

4th international conference on Intelligent Circuits and Systems, ICICS 2022

作者： Arora, Sneha Tripathi, Suman Lata VLSI Design School of Electronics and Electrical Engineering Lovely Professional University Punjab Phagwara India

Graphene nano ribbon field effect transistor is an emerging field of research in VLSI technology beyond 32nm. VLSI main motive is to reduce power consumption and other parameters such as delay, PDP (power delay product) to improve the efficiency. this article discusses the requirement for high-performance applications that use little power. However, employing low-power devices for high-rank applications such as microprocessors, digital signal processors, and static random-access memory (SRAM) is very challenging. In the field of memory design and logical circuit design, it is well recognised that the Decoder plays a crucial role. As part of the planned work in 22nm technology, a technique has been developed for evaluating the parameters Power delay product, Energy delay product, Power consumption, and Delay on 14T and 15T based employing 2 to 4 decoders based on MOSFET and GNRFET. So, the final proposed circuit is obtained by application of decoders with the use of GNRFET while improving the performance parameters. © Published under licence by IOP Publishing Ltd.

关键词： Decoding

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