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检索条件"任意字段=14th International Conference on Field-Programmable Logic and Applications"

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Multi-Level Single Event Effect-hardened Design for SRAM-FPGA-Based System

Multi-Level Single Event Effect-hardened Design for SRAM-FPG...

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international conference on Reliability, Maintainability and Safety,ICRMS

作者： Wenbin Zhang Peng Li Peng Guo Yifan Chen Technology and Engineering Center for Space Utilization Chinese Academy of Sciences Beijing P.R. China School of Control and Computer Engineering North China Electric Power University Beijing P.R. China

ISBN: (数字)9798350329988

ISBN: (纸本)9798350329995

Commercial off-the-shelf (COTS) static random-access memory (SRAM) based field-programmable gate arrays (FPGAs) technology has been widely used within the space industry due to its cost-effectiveness and high-performance attributes. However, its original design primarily caters to benign operating environments. the deleterious impact of space radiation, particularly the single-event effect (SEE), poses a significant threat to the operational reliability of SRAM-FPGA devices in space applications. In order to fortify these devices against the challenges of the space radiation environment and ensure the utmost system reliability, this paper initiates by providing an overview of the SEE-related issues pertaining to SRAM-FPGA and offers insights into general hardening design solutions. Subsequently, this paper introduces a comprehensive multilevel SEE hardening design strategy, encompassing component selection, as well as hardware and software hardening methods at the board-level. Furthermore, it delves into system-level design protective measures. A real-world case study is presented to exemplify the practical implementation of these hardening techniques that enhance system reliability.

关键词： Radiation hardening (electronics) Prevention and mitigation Design methodology Space radiation Reliability engineering Software Hardware Reliability Integrated circuit reliability field programmable gate arrays

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Research on the FPGA Implementation of the SM4 Algorithm

Research on the FPGA Implementation of the SM4 Algorithm

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international conference on Machine Learning, Big Data and Business Intelligence (MLBDBI)

作者： Tianyao Li Xianwei Gao Qian Cheng Yitong Li Beijing Electronic Science and Technology Institute Beijing China

ISBN: (数字)9798331541798

ISBN: (纸本)9798331505615

the SM4 algorithm is a symmetric key block cipher that uses a Feistel structure and is widely applied in the confidentiality of information and data. this paper explores the process and performance evaluation of implementing the SM4 symmetric encryption algorithm on an FPGA platform. As a national standard encryption algorithm in China, SM4 is widely used for data protection and information security. In this study, we utilized Quartus II software for design and simulation, and ModelSim for verification, ensuring the correctness and efficiency of the algorithm implementation. In the experiments, we employed the 5AGXFB3H4F35I3 FPGA device to implement the core functionalities of the SM4 algorithm. through reasonable allocation of logic resources, we optimized the balance between speed and efficiency. the experimental results demonstrate that the implemented SM4 algorithm can effectively perform encryption tasks on the FPGA platform. this research provides strong support for the hardware acceleration of the SM4 algorithm in practical applications, which demonstrated the wide range of applications of FPGA in the field of information security.

关键词： Performance evaluation Machine learning algorithms Quantum computing Protocols Software algorithms Information security Data protection Software Encryption field programmable gate arrays

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A FPGA Embedded DSP Supporting Parallel Multiple Low Bit-Width Multiply-Accumulate Operations 10

A FPGA Embedded DSP Supporting Parallel Multiple Low Bit-Wid...

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10th international conference on Industrial Engineering and applications, ICIEA 2023

作者： Wang, Miao Huang, Zhihong Cai, Gang Wang, Junxuan School of Communications and Information Engineering Xi'an University of Posts and Telecommunications Xi'an710121 China Aerospace Information Research Institute Chinese Academy of Sciences Ehiway Microelectronic Science and Technology Co.Ltd. Beijing100094 China

ISBN: (纸本)9781643684086

With the continuous development of big data and hardware computing platforms, deep learning has been substantially applied in many intelligent scenarios. Recent studies have shown that using low bit-width networks in deep learning inference can effectively improve the overall performance of accelerator by reducing the computational ability requirements while maintaining the recognition accuracy of accelerator. Among them, low bit-width convolutional operations such as 8bit and 4bit are widely used in applications such as graph recognition. FPGA chip is the core key device of digital system, due to the excellent reconfigurability of FPGA, it has become one of the mainstream platforms in the field of deep learning accelerator. the current mainstream FPGAs are composed of higher bit-width multipliers due to the need to adapt to different computing application requirements, and the DSP module resources are used to perform low bit-width convolutional operations, which only occupy part of the multiplier bit-width, thus wasting a large amount of hardware on chip resources. therefore, this paper proposes a DSP architecture of using large bit-width multipliers to compute low bit-width multiplications in parallel, so that the new DSP can realize double 8bit and 4bit multiply-accumulate operations without adding multipliers, and can support any combination of signed and unsigned data operations. the design is based on the commercial Stratix IV DSP architecture, and the overall circuit is designed with SMIC 14nm standard CMOS process. the experimental results show that when calculating the same number of 4-bit and 8-bit multiply-accumulate operations, the resource consumption area of the improved DSP is reduced by 43.5% and the speed is increased by 48%. © 2023 the authors and IOS Press.

关键词： field programmable gate arrays (FPGA)

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Design and Implementation of Matched Filtering and Timing Recovery Algorithm for IEEE 802.15.4 Digital Baseband Front End 5th

Design and Implementation of Matched Filtering and Timing Re...

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5th international conference on VLSI, Communication and Signal Processing, VCAS 2022

作者： Shukla, Preeti Tiwari, Manish Mohanasundaram Haribabu, P. Motilal Nehru National Institute of Technology Allahabad Prayagraj India Centre for Development of Advanced Computing Bangalore India

ISBN: (纸本)9789819909728

IEEE 802.15.4 is a technical standard for low-rate wireless personal area network for long range communication. this standard provides a framework for the lower layers (PHY and MAC) in the OSI model for wireless connectivity network which is used in IoT applications. In a communication network, channel noise and timing mismatch are common problems. In order to recover the received signal successfully, a receiver should be able to overcome these problems. Demodulation and demapping alone would not be able to serve the purpose. this paper proposes modeling, design, and simulation of signal conditioning blocks in the receiver for O-QPSK PHY and SUN O-QPSK PHY mentioned in the standard. these blocks process the signal available at the digital baseband front end of the receiver which is available after RF to analog baseband down conversion and analog baseband to digital baseband conversion. Signal conditioning introduced in this work involves the design of matched filter and timing recovery to overcome the noise and sampling time mismatch. these blocks along with the O-QPSK transceiver have been first modeled in MATLAB/Simulink. logic design for the modules introduced in the receiver chain has been implemented using Verilog RTL and verified through simulation. For FPGA implementation, RTL modules of matched filter and timing recovery have been integrated at the output of ADC, and output of timing recovery goes for inverse pulse shaping and is fed to O-QPSK and smart utility network (SUN) O-QPSK demodulator of receiver chain. All the modules are implemented on the FPGA Board Xilinx UltraScale + VCU118. © 2023, the Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.

关键词： field programmable gate arrays (FPGA)

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An AI-Based Classroom Monitoring System Leveraging Computer Vision and Machine Learning

An AI-Based Classroom Monitoring System Leveraging Computer ...

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international Bhurban conference on Applied Sciences & Technology, IBCAST

作者： Nofil Siddiqui Maaz Khalid Ayza Ahmed Abdul Aleem Muhammad Irfan Waqar Ahmad Fahad Bin Muslim Faculty of Electrical Engineering GIK Institute Swabi Pakistan Faculty of Computer Science and Engineering GIK Institute Swabi Pakistan

ISBN: (数字)9798350308259

ISBN: (纸本)9798350308266

this paper presents an AI-based classroom monitoring system utilizing computer vision and machine learning. the system employs Multi-Task Cascaded Convolutional Neural Networks (MTCNN) for face detection, FaceNet for facial recognition, and a CNN model trained on the Facial Expression Recognition (FER) 2013 dataset for emotional analysis. A novel heterogeneous approach combines field programmable Gate Arrays (FPGA) and a central processor to overcome the limitations of BRAM and complex computation constraints. Evaluation in real-world classrooms yielded a promising 70% accuracy in emotion detection, marking a significant stride in the field. this research not only advances AI-based monitoring systems but also indicates potential applications in surveillance and security.

关键词： Emotion recognition Face recognition Surveillance Machine learning logic gates Multitasking Convolutional neural networks Security Face detection field programmable gate arrays

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Personalization in Practice: Methods and applications 21

Personalization in Practice: Methods and Applications

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14th ACM international conference on Web Search and Data Mining (WSDM)

作者： Goldenberg, Dmitri Kofman, Kostia Albert, Javier Mizrachi, Sarai Horowitz, Adam Teinemaa, Irene Booking Com Tel Aviv Israel Booking Com Amsterdam Netherlands

ISBN: (纸本)9781450382977

Personalization is one of the key applications in machine learning with widespread usage across e-commerce, entertainment, production, healthcare and many other industries. While various machine learning techniques present novel state-of-the-art advances and super-human performance year-over-year, personalization and recommender-systems applications are often late-adopters of novel solutions due to problem hardness and implementation complexity. this tutorial presents recent advances across the personalization industry and demonstrates their practical applications in real case-studies of world-leading online platforms. Key trends such as deep learning, causality and active exploration with bandits are depicted with real examples and demonstrated alongside their business considerations and implementation challenges. Rising topics like explainability, fairness, natural interfaces and content generation are covered, touching on aspects of both technology and user experience. Our tutorial relies on recent advances in the field and on work conducted at *** , where we implement personalization models on one of the world's leading online travel platform.

关键词： Personalization Causality Deep Learning Recommender Systems Active Exploration Natural Experience Content Generation Fairness Explainability Uplift Modeling

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Artificial Intelligence in Music Education: Exploring applications, Benefits, and Challenges

Artificial Intelligence in Music Education: Exploring Applic...

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international conference on Educational and Information Technology (ICEIT)

作者： Yuanyang Yue Yunqi Jing School of Education Shanghai Normal University Tianhua College Shanghai China

ISBN: (数字)9798331540883

ISBN: (纸本)9798331540890

this research investigates the present scenario of developments in artificial intelligence in music education in general and in various methods used to improve pedagogical practice as well as approaches that have developed in this field. the analysis is on benefits of integrating AI on teaching music on adapted learning experience, automated processes of assessments, and greater accessibility. It also takes into consideration challenges of integrating AI on teaching music on technological limitations, issues of ethics, and how teaching professionals can remain professional through continuing educations on ongoing bases. the conclusion is on offering ideas on how to carry out its research on its future along with real life implementation within this new body of literature.

关键词： Learning systems Continuing education Ethics Reviews Education Buildings Collaboration Software Artificial intelligence Information technology

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14th international conference on Graph Transformation, ICGT 2021 Held as Part of Software Technologies: applications and Foundations, STAF 2021

14th International Conference on Graph Transformation, ICGT ...

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14th international conference on Graph Transformation, ICGT 2021 Held as Part of Software Technologies: applications and Foundations, STAF 2021

ISBN: (纸本)9783030789459

the proceedings contain 16 papers. the special focus in this conference is on Graph Transformation. the topics include: Rule-Based Top-Down Parsing for Acyclic Contextual Hyperedge Replacement Grammars;preface;concurrency theorems for Non-linear Rewriting theories;nets with Mana: A Framework for Chemical Reaction Modelling;a Case Study on the Graph-Transformational Modeling and Analysis of Puzzles;interval Probabilistic Timed Graph Transformation Systems;verifying Graph Programs with Monadic Second-Order logic;on the Complexity of Simulating Probabilistic Timed Graph Transformation Systems;automated Checking and Completion of Backward Confluence for Hyperedge Replacement Grammars;grapePress - A Computational Notebook for Graph Transformations;a Generalized Concurrent Rule Construction for Double-Pushout Rewriting;transformations of Reaction Systems Over Categories by Means of Epi-Mono Factorization and Functors;Graph Rewriting and Relabeling with PBPO +;incorrectness logic for Graph Programs.

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Design of Modified Booth Multiplier Based on field programmable Gate Array 16th

Design of Modified Booth Multiplier Based on Field Programma...

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16th international conference on Intelligent Information Hiding and Multimedia Signal Processing, IIH-MSP 2020 in conjunction with the 13th international conference on Frontiers of Information Technology, applications and Tools, FITAT 2020

作者： Jigjidsuren, Battogtokh Badarch, Zorig Sukhbaatar, Jamiyan Namsrai, Oyun-Erdene Department of Electronics and Communication Engineering National University of Mongolia Ulaanbaatar Mongolia

ISBN: (纸本)9789813367562

In the field of digital signal processing, multiplication is an important and computationally intensive operation. Modified Booth algorithm is a crucial improvement in the binary multiplication. Here, we used Wallace tree algorithm which increased the speed of multiplier operation. Modified Booth encoder utilizes the minimum logic gates and reduces chip area. Design of this multiplier uses VHDL and simulates using Xilinx ISE software. the multiplier has been implemented on Spartan 3E fpga chip. © the Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2021.

关键词： logic gates

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Determination of Channel Parameters of FinFET using Artificial Neural Networks in Current Mirror applications

Determination of Channel Parameters of FinFET using Artifici...

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international conference on Electrical and Electronics Engineering, ELECO

作者： Mücahit Osman Kağnici Sinem Keleş Department of Electrical and Electronics Engineering Istanbul Medeniyet University Istanbul Turkey

Short channel effects are seen in planar MOSFET and CMOS transistors with a size smaller than 50nm. the Fin field-Effect Transistor (FinFET) was developed in response to MOSFET transistors as the size decreased below 50nm. this has resulted in reduced power consumption and less short channel effects. the transition from MOSFET transistor to FinFET technology brings challenges such as complex design and rapid increase in resistance. this challenge will require the designer to determine the values of the FinFET transistor channel parameters entirely by his/her own experience. the aim of this study is to design an artificial neural network model to obtain acceptable and successful channel width and channel length values of the FinFET transistor to be determined by the circuit designer. For the test of the designed model, cascode current mirror and Wilson current mirror are considered in this study.

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