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14th international workshop on power and timing modeling, optimization and simulation, patmos 2004

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14th international workshop on power and timing modeling, optimization and simulation, patmos 2004

ISBN: (纸本)3540230955

the proceedings contain 92 papers. the special focus in this conference is on Buses and Communication. the topics include: Connecting e-dreams to deep-submicron realities;design methodology for rapid development of SoC ICs based on an innovative system architecture with emphasis to timing closure and power consumption optimization;nick kanopoulos;adaptive subthreshold leakage reduction through N/P wells reverse biasing;leakage in CMOS circuits;randomness in nanometer design;crosstalk cancellation for realistic PCB buses;a low-power encoding scheme for gigabyte video interfaces;dynamic wire delay and slew metrics for integrated bus structures;perfect 3-limited-weight code for low power I/O;a high-level DSM bus model for accurate exploration of transmission behaviour and power estimation of global system buses;performance metric based optimization protocol;temperature dependence in low power CMOS UDSM process;yield optimization by means of process parameters estimation;high yield standard cell libraries;a study of crosstalk through bonding and package parasitics in CMOS mixed analog-digital circuits;sleepy stack reduction of leakage power;a cycle-accurate energy estimator for CMOS digital circuits;leakage reduction at the architectural level and its application to 16 bit multiplier architectures;reducing cross-talk induced power consumption and delay;investigation of low-power low-voltage circuit techniques for a hybrid full-adder cell;leakage power analysis and comparison of deep submicron logic gates;threshold mean larger ratio motion estimation in MPEG encoding using LNS and energy- and area-efficient deinterleaving architecture for high-throughput wireless applications.

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Design methodology for rapid development of SoC ICs based on an innovative system architecture with emphasis to timing closure and power consumption optimization 14th

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14th international workshop on power and timing modeling, optimization and simulation (patmos 2004)

作者： Kanopoulos, N Atmel Corp Multimedia & Commun Morrisville NC 27560 USA

ISBN: (纸本)3540230955

Complex System on Chip (SoC) ICs require a high development effort and extensive testing in order to meet performance and power consumption specifications. those requirements are usually achieved through laborious and iterative procedures which engage synthesis, timing, power analysis and back-end tools. Traditional design methodologies deal with the above issues from a synthesis or technology point of view, trying to optimize the propagation delay of primitive cells, simplifying the logic and disabling the clocks when possible. this presentation describes how a design methodology can be combined with an innovative architecture, called COMBA, for system on chip ICs in order to help the designer to achieve timing closure and meet performance and power consumption requirements in short time. this methodology is supported by tools that produce the gate level description of the system using pre-optimized building blocks for the COMBA architecture, leading to minimum development and testing time while preserving the performance and power requirements.

关键词： System-on-chip

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Discrete-event modeling and simulation of superscalar microprocessor architectures

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14th international workshop on power and timing modeling, optimization and simulation (patmos 2004)

作者： Brandolese, C Fornaciari, W Salice, F Politecn Milan I-20133 Milan Italy

ISBN: (纸本)3540230955

this paper presents a methodology and framework to model the behavior of superscalar microprocessors. the simulation is focused on timing analysis and ignores all functional aspects. the methodology also provides a framework for building new simulators for generic architectures. the results obtained show a good accuracy and a satisfactory computational efficiency. Furthermore, the C++ SDK allows rapid development of new processor models making the methodology suitable for design space exploration over new processor architectures.

关键词： Computational efficiency

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Automatic Design of Arbitrary-Size Approximate Sorting Networks with Error Guarantee 26

Automatic Design of Arbitrary-Size Approximate Sorting Netwo...

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26th international workshop on power and timing modeling, optimization and simulation (patmos)

作者： Mrazek, Vojtech Vasicek, Zdenek Brno Univ Technol Fac Informat Technol Ctr Excellence IT4Innovat Brno Czech Republic

ISBN: (纸本)9781509007332

Despite the fact that hardware sorters offer great performance, they become expensive as the number of inputs increases. In order to address the problem of high-performance and power-efficient computing, we propose a scalable method for construction of power-efficient sorting networks suitable for hardware implementation. the proposed approach exploits the error resilience which is present in many real-world applications such as digital signal processing, biological computing and large-scale scientific computing. the method is based on recursive construction of large sorting networks using smaller instances of approximate sorting networks. the design process is tunable and enables to achieve desired tradeoffs between the accuracy and power consumption or implementation cost. A search-based design method is used to obtain approximate sorting networks. To measure and analyze the accuracy of approximate networks, three data-independent quality metrics are proposed. Namely, guarantee of error probability, worst-case error and error distribution are discussed. A significant improvement in the implementation cost and power consumption was obtained. For example, 20% reduction in power consumption was achieved by introducing a small error in 256-input sorter. the difference in rank is proved to be not worse than 2 with probability at least 99%. In addition to that, it is guaranteed that the worst-case difference is equal to 6.

关键词： Electric power utilization

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Two level compact simulation methodology for timing analysis of power-switched circuits

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14th international workshop on power and timing modeling, optimization and simulation (patmos 2004)

作者： Henzler, S Georgakos, G Berthold, J Schmitt-Landsiedel, D Tech Univ Munich D-80290 Munich Germany Infineon Technol AG Corp Log D-81541 Munich Germany

ISBN: (纸本)3540230955

Standby-power dissipation in ultra-deep submicron CMOS can be reduced by power switching. As the cut-off device has a strong impact on area consumption, minimum power-down time, signal delay and leakage suppression, a proper sizing of this device is of general importance. therefore a two level compact simulation methodology is proposed which provides fast and accurate CAD support to the switch design task.

关键词： Computer aided design

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Noise margin in low power SRAM cells

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14th international workshop on power and timing modeling, optimization and simulation (patmos 2004)

作者： Cserveny, S Masgonty, JM Piguet, C CESM SA Neuchatel Switzerland

ISBN: (纸本)3540230955

Noise margin at read, at write and in stand-by is analyzed for the 6 transistor SRAM cell in a 0.18 mum process considering specific low power conditions such as low supply voltage and source-body biasing. these conditions reduce the noise margin. By using an asymmetrical cell design in which read is performed only on one of the two complementary bit lines, the noise margin can be improved and the bias limits extended for a reduced power consumption.

关键词： Static random access storage

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PMHLS 2.0: An Automated optimization of power Management During High-Level Synthesis 26

PMHLS 2.0: An Automated Optimization of Power Management Dur...

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26th international workshop on power and timing modeling, optimization and simulation (patmos)

作者： Macko, Dominik Slovak Univ Technol Bratislava Fac Informat & Informat Technol Bratislava Slovakia

ISBN: (纸本)9781509007332

Design automation is very important in modern systems-on-chip development, complexity of which is ever growing. the most crucial issue in highly integrated systems is the increased power density and the corresponding temperature problems influencing reliability. therefore, the power must be managed in such systems. power management enables to implement various power-reduction techniques, such as power gating, multiple voltages, or voltage and frequency scaling. However, the automation of power-management design starts at the register-transfer level. Only the recent research begins to adopt power management at the system level of abstraction, which is increasingly used in the industry as a design starting point. In this paper, we propose an enhanced automation of the design process by using the optimized power-management high-level synthesis. this method transforms the system-level power-management specification to the traditionally used form at the register-transfer level. We have implemented this method to a tool called PMHLS, which automates the whole process. It uses optimization decisions to resolve some kinds of inconsistencies and thus makes the power management more efficient. this automation helps to reduce the number of human errors, potentially introduced by a designer during manual design. It also significantly speeds up the system development process. the benefits of the proposed method and the implemented design-automation tool are supported by the experimental results.

关键词： design automation high-level synthesis low power power management specification

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Leakage in CMOS circuits - An introduction

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14th international workshop on power and timing modeling, optimization and simulation (patmos 2004)

作者： Helms, D Schmidt, E Nebel, W ChipVis Design Syst AG D-26121 Oldenburg Germany

ISBN: (纸本)3540230955

In this tutorial, we give an introduction to the increasingly important effect of leakage in recent and upcoming technologies. the sources of leakage such as subthreshold leakage, gate leakage, pn-junction leakage and further GIDL, hot-carrier effect and punchthrough are identified and analyzed separately and also under PTV variations. Since leakage will dominate power consumption in future technologies, we also review leakage optimization techniques and leakage estimation approaches supporting optimizations especially at higher abstraction levels.

关键词： timing circuits

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A generic timing mechanism for using the APPLES gate-level simulator in a mixed-level simulation environment

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14th international workshop on power and timing modeling, optimization and simulation (patmos 2004)

作者： Maili, A Dalton, D Steger, C UCD Dept Comp Sci Dublin 4 Ireland Graz Univ Technol Inst Tech Informat A-8010 Graz Austria

ISBN: (纸本)3540230955

In this paper, we describe a generic timing mechanism, which allows building mixed-level simulation environments that facilitate timing closure for their gate-level modules whilst simulating a whole System-on-Chip (SoC) made of modules at different levels of abstraction. the APPLES gate level accelerator provides fast timing-accurate simulation of gate-level designs. But to enable its use for large SoC-designs, a generic timing mechanism must be developed in order to use the APPLES processor in a mixed-level environment together with higher-level simulation engines. the environment we present here makes use of a universal time mechanism and a flexible client-server implementation to enable a generic and expandable system for mixed-level, mixed-language timing simulation.

关键词： System-on-chip

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A high-level DSM bus model for accurate exploration of transmission behaviour and power estimation of global system buses

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14th international workshop on power and timing modeling, optimization and simulation (patmos 2004)

作者： Kretzschmar, C Bitterlich, T Müller, D Tech Univ Chemnitz Dpt Syst & Circuit Design D-09126 Chemnitz Germany

ISBN: (纸本)3540230955

Deep sub-micron effects influence the signal transmission especially on global wires. In order to select communication architectures, minimize power dissipation and improve signal integrity it is necessary to explore DSM effects already at high levels of design abstraction. therefore in this paper we present a parameterized high-level simulation model which is based on SPICE simulations and evaluates therefore signal integrity and power dissipation very accurately. the maximum error of our model was 1.3%. In comparism to a full SPICE simulation the required computation time could be reduced by a factor of up to 900.

关键词： Electric losses

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