检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

265 篇 会议
28 篇 期刊文献

馆藏范围

293 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

229 篇 工学
- 218 篇 计算机科学与技术...
- 126 篇 软件工程
- 100 篇 电子科学与技术（可...
- 70 篇 电气工程
- 31 篇 信息与通信工程
- 12 篇 动力工程及工程热...
- 11 篇 机械工程
- 11 篇 控制科学与工程
- 6 篇 土木工程
- 6 篇 生物工程
- 5 篇 建筑学
- 4 篇 仪器科学与技术
- 4 篇 冶金工程
- 4 篇 生物医学工程（可授...
- 2 篇 材料科学与工程（可...
- 2 篇 化学工程与技术
- 1 篇 纺织科学与工程
- 1 篇 农业工程
93 篇 理学
- 74 篇 数学
- 13 篇 物理学
- 9 篇 统计学（可授理学、...
- 7 篇 生物学
- 5 篇 系统科学
- 1 篇 化学
18 篇 管理学
- 15 篇 管理科学与工程(可...
- 8 篇 工商管理
- 3 篇 图书情报与档案管...
4 篇 经济学
- 4 篇 应用经济学
3 篇 教育学
- 3 篇 教育学
1 篇 法学
- 1 篇 社会学
1 篇 农学
1 篇 医学

主题

155 篇 field programmab...
79 篇 field programmab...
22 篇 hardware
13 篇 computer archite...
7 篇 routing
7 篇 costs
7 篇 clocks
7 篇 delay
6 篇 fpga
5 篇 real time system...
5 篇 switches
5 篇 circuit testing
5 篇 circuits
5 篇 field-programmab...
4 篇 table lookup
4 篇 programmable log...
4 篇 fpgas
4 篇 application soft...
4 篇 signal processin...
4 篇 reconfigurable l...

机构

4 篇 univ british col...
4 篇 univ of toronto
3 篇 univ of toronto ...
3 篇 northwestern uni...
3 篇 computer science...
3 篇 altera corporati...
3 篇 intel corporatio...
2 篇 department of ee...
2 篇 politecn torino ...
2 篇 department of el...
2 篇 microsemi corp s...
2 篇 imperial college...
2 篇 university of br...
2 篇 ustc dept comp s...
2 篇 univ hong kong d...
2 篇 univ of californ...
2 篇 information scie...
2 篇 univ calif berke...
2 篇 edward s. rogers...
2 篇 univ of californ...

作者

11 篇 rose jonathan
8 篇 wawrzynek john
7 篇 cong jason
6 篇 hauck scott
5 篇 wilton steven j....
5 篇 betz vaughn
4 篇 dehon andre
4 篇 wilton steven j....
3 篇 ienne paolo
3 篇 wong d.f.
3 篇 kent kenneth b.
3 篇 li fei
3 篇 prasanna viktor ...
3 篇 mishchenko alan
3 篇 brayton robert
3 篇 chow paul
3 篇 brisk philip
3 篇 parandeh-afshar ...
2 篇 li xi
2 篇 sun fan

语言

293 篇 英文

检索条件"任意字段=15th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 293 条记录，以下是1-10 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Quality-driven Design Methodology for PUFs in FPGAs for Secure IoT 24

Quality-driven Design Methodology for PUFs in FPGAs for Secu...

引用

24th international symposium on Quality Electronic Design (ISQED)

作者： Wang, Xiangyun Song, Yicheng Prakash, Katyayani Zilic, Zeljko Langsetmo, Tomas McGill Univ Montreal PQ Canada KNOX Ind Inc Montreal PQ Canada

ISBN: (纸本)9798350334753

the emergence of Internet of things (IoT) has placed strong emphasis on security. Physical Unclonable Functions (PUFs) are a promising low-cost security solution for IoT. Since field-programmable gate arrays (FPGAs) are more trusted than custom Integrated Circuits (ICs) in building secure systems, implementing PUFs in FPGAs is appealing. In this paper, we propose a methodology for improving the quality of delay-based PUFs on FPGAs. With our method, an asymmetric delay-based PUF has been predictably designed for temperature- and aging-independent operation. Furthermore, the resistance to modeling attacks is built into the design.

关键词： Physical Unclonable Function (PUF) Internet-of-things (IoT) field-programmable gate Array (FPGA) Hardware Security Design Methodology

来源：评论

学校读者我要写书评

暂无评论

FPIA: field-programmable Ising arrays with In-Memory Computing 24

FPIA: Field-Programmable Ising Arrays with In-Memory Computi...

引用

29th acm/IEEE international symposium on Low Power Electronics and Design, ISLPED 2024

作者： Hutchinson, George Higgins Sifferman, Ethan Bhattacharya, Tinish Kwon, Dongseok Strukov, Dmitri B Department of Electrical and Computer Engineering University of California at Santa Barbara Santa BarbaraCA United States

ISBN: (纸本)9798400706882

Ising Machines, a promising approach for solving combinatorial optimization problems, are naturally suited for energy-saving and compact in-memory computing implementations with emerging memories. A naïve in-memory computing implementation of a quadratic Ising Machine requires an array of coupling weights that grows quadratically with problem size. this approach, however, uses resources inefficiently due to the inherent sparsity of practical optimization problems. We first show that this issue can be addressed by partitioning a coupling array into smaller sub-arrays. this technique, however, requires interconnecting sub-arrays, which incurs overhead. In response, we present FPIA, an in-memory computing architecture for quadratic Ising Machines inspired by island-type field programmable gate arrays. We adapt open-source tools to optimize problem embedding and model overhead. Modeling results of benchmark problems for the developed architecture show up to 10x increase in density and speed compared to the baseline approach. Finally, we discuss algorithm/circuit co-design techniques for further improvements. © 2024 Copyright is held by the owner/author(s). Publication rights licensed to acm.

关键词： Ising model

来源：评论

学校读者我要写书评

暂无评论

Accounting for Floorplan Irregularity and Configuration Dependence in FPGA Routing Delay Models 24

Accounting for Floorplan Irregularity and Configuration Depe...

引用

24th international symposium on Quality Electronic Design (ISQED)

作者： Barajas, Gabriel Greene, Jonathan W. Li, Fei Tandon, James Microchip San Jose CA 95134 USA Cambios Comp LLC Palo Alto CA USA Calif State Univ East Bay Hayward CA USA

ISBN: (纸本)9798350334753

Accurate delay estimates for a user application implemented in a field-programmable gate Array (FPGA) are essential for a quality FPGA timing flow and to avoid leaving performance on the table. FPGA inter-cluster routing consists of wire segments of a limited number of types which repeat in a somewhat regular pattern, interconnected by configurable muxes. the delay at any fanout of a segment can be significantly impacted by configuration-dependent capacitive loading related to other fanouts. Also, the insertion of RAM and math blocks into the FPGA floorplan introduces irregular stretching of the wire segments, altering their delays. We explain why and how commercial FPGA software typically employs a parameterized model for the delay at each fanout of a segment, based on the configuration and the irregularities present, with the parameters determined by fitting SPICE simulation data for a representative sample of cases. We propose incorporating readily-computed common path resistance values into the model. this enables high accuracy with fewer parameters and without the large amounts of SPICE data that would otherwise be required to explore interactions between floorplan irregularities and the set of active fanouts. In combination with other features of our models, errors in segment delay are reduced by almost half.

关键词： field-programmable gate arrays FPGAs delay estimation Elmore delay common path resistance

来源：评论

学校读者我要写书评

暂无评论

Online Training from Streaming Data with Concept Drift on FPGAs 24

Online Training from Streaming Data with Concept Drift on FP...

引用

24th international symposium on Quality Electronic Design (ISQED)

作者： Roorda, Esther Wilton, Steven J. E. Univ British Columbia Vancouver BC Canada

ISBN: (纸本)9798350334753

In dynamic environments, the inputs to machine learning models may exhibit statistical changes over time, through what is called concept drift. Incremental training can allow machine learning models to adapt to changing conditions and maintain high accuracy by continuously updating network parameters. In the context of FPGA-based accelerators however, online incremental learning is challenging due to resource and communication constraints, as well as the absence of labelled training data. these challenges have not been fully evaluated or addressed in existing research. In this paper, we present and evaluate strategies for performing incremental training on streaming data with concept drift on FPGA-based platforms. We first present FPGA-based implementations of existing training algorithms to demonstrate the viability of online training with concept shift and to evaluate design tradeoffs. We then propose a technique for online training without labelled data and demonstrate its potential in the context of FPGA-based hardware acceleration.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Extending Memory Compatibility with Yosys Front-End in the VTR Flow 34

Extending Memory Compatibility with Yosys Front-End in the V...

引用

34th international Workshop on Rapid System Prototyping - Shortening the Path from Specification to Prototype

作者： Azadi, Alireza Arjomand, Amir Kent, Kenneth B. Univ New Brunswick Fredericton NB Canada

ISBN: (纸本)9798400704109

Verilog-to-routing (VTR) is an open source Computer Aided Design (CAD) framework that is widely used for research purposes. VTR provides researchers with a comprehensive set of benchmarks and FPGA architectures to test, compare and verify their designs and CAD algorithms. VTR employs Odin, Yosys and a combination of Yosys+Odin as its front-ends for elaborating digital designs written in Verilog. Yosys is a standalone synthesis framework that is maintained separately. In order to take advantage of Yosys' latest upgrades, it is essential to upgrade VTR in tandem with Yosys to keep up with its latest changes. In our study, we investigated the integration of the latest available version of Yosys into VTR. In the course of this research, we encountered a challenge stemming from a memory incompatibility in newer versions of Yosys. Our primary research question became how to effectively facilitate netlist conversion from Yosys to Odin to overcome this incompatibility issue. We then showcase how this upgrade affects our benchmark suite, highlighting the notable changes in circuit quality and the tool performance. Our post-upgrade evaluations reveal that the STA (static timing analysis) time of placement and the placement time itself exhibited improvements of up to 11.53% and 10.43%, respectively.

关键词： field programmable gate arrays Electronic Design Automation Free and Open Source Software Yosys Verilog to Routing

来源：评论

学校读者我要写书评

暂无评论

Accelerating SSSP for Power-Law Graphs 22

Accelerating SSSP for Power-Law Graphs

引用

2022 acm/sigda international symposium on field-programmable gate arrays, FPGA 2022

作者： Chi, Yuze Guo, Licheng Cong, Jason University of California Los Angeles Los AngelesCA United States

ISBN: (纸本)9781450391498

the single-source shortest path (SSSP) problem is one of the most important and well-studied graph problems widely used in many application domains, such as road navigation, neural image reconstruction, and social network analysis. Although we have known various SSSP algorithms for decades, implementing one for large-scale power-law graphs efficiently is still highly challenging today, because - a work-efficient SSSP algorithm requires priority-order traversal of graph data, - the priority queue needs to be scalable both in throughput and capacity, and - priority-order traversal requires extensive random memory accesses on graph data. In this paper, we present SPLAG to accelerate SSSP for power-law graphs on FPGAs. SPLAG uses a coarse-grained priority queue (CGPQ) to enable high-throughput priority-order graph traversal with a large frontier. To mitigate the high-volume random accesses, SPLAG employs a customized vertex cache (CVC) to reduce off-chip memory access and improve the throughput to read and update vertex data. Experimental results on various synthetic and real-world datasets show up to a 4.9× speedup over state-of-the-art SSSP accelerators, a 2.6× speedup over 32-thread CPU running at 4.4 GHz, and a 0.9× speedup over an A100 GPU that has 4.1× power budget and 3.4× HBM bandwidth. Such a high performance would place SPLAG in the 14th position of the Graph 500 benchmark for data intensive applications (the highest using a single FPGA) with only a 45 W power budget. SPLAG is written in high-level synthesis C++ and is fully parameterized, which means it can be easily ported to various different FPGAs with different configurations. © 2022 acm.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond 24

HLSFactory: A Framework Empowering High-Level Synthesis Data...

引用

6th international symposium on Machine Learning for CAD (MLCAD)

作者： Abi-Karam, Stefan Sarkar, Rishov Seigler, Allison Lowe, Sean Wei, Zhigang Chen, Hanqiu Rao, Nanditha John, Lizy Arora, Aman Hao, Cong Georgia Inst Technol Atlanta GA 30332 USA Georgia Tech Res Inst Atlanta GA 30332 USA Univ Texas Austin Austin TX USA Arizona State Univ Tempe AZ USA Int Inst Informat Technol Bangalore Bangalore Karnataka India

ISBN: (数字)9798350363562

ISBN: (纸本)9798400706998

Machine learning (ML) techniques have been applied to high-level synthesis (HLS) flows for quality-of-result (QoR) prediction and design space exploration (DSE). Nevertheless, the scarcity of accessible highquality HLS datasets and the complexity of building such datasets present great challenges to FPGA and ML researchers. Existing datasets either cover only a subset of previously published benchmarks, provide no way to enumerate optimization design spaces, are limited to a specific vendor, or have no reproducible and extensible software for dataset construction. Many works also lack user-friendly ways to add more designs to existing datasets, limiting wider adoption and sustainability of such datasets. In response to these challenges, we introduce HLSFactory, a comprehensive framework designed to facilitate the curation and generation of high-quality HLS design datasets. HLSFactory has three main stages: 1) a design space expansion stage to elaborate single HLS designs into large design spaces using various optimization directives across multiple vendor tools, 2) a design synthesis stage to execute HLS and FPGA tool flows concurrently across designs, and 3) a data aggregation stage for extracting standardized data into packaged datasets for ML usage. this tripartite architecture not only ensures broad coverage of data points via design space expansion but also supports interoperability with tools from multiple vendors. Users can contribute to each stage easily by submitting their own HLS designs or synthesis results via provided user APIs. the framework is also flexible, allowing extensions at every step via user APIs with custom frontends, synthesis tools, and scripts. To demonstrate the framework functionality, we include an initial set of built-in base designs from PolyBench, MachSuite, Rosetta, CHStone, Kastner et al.'s Parallel Programming for FPGAs, and curated kernels from existing open-source HLS designs. We report the statistical analyses and design space

关键词： Solid modeling Statistical analysis Buildings Machine learning Benchmark testing Software Space exploration Sustainable development field programmable gate arrays Optimization

来源：评论

学校读者我要写书评

暂无评论

Folded integer multiplication for fpgas 21

Folded integer multiplication for fpgas

引用

2021 acm/sigda international symposium on field-programmable gate arrays, FPGA 2021

作者： Langhammer, Martin Pasca, Bogdan Intel Corporation Salisbury United Kingdom Intel Corporation France

ISBN: (纸本)9781450382182

Encryption-especially the key exchange algorithms such as RSA-is an increasing use-model for FPGAs, driven by the adoption of the FPGA as a SmartNIC in the datacenter. While bulk encryption such as AES maps well to generic FPGA features, the very large multipliers required for RSA are a much more difficult problem. Although FPGAs contain thousands of small integer multipliers in DSP Blocks, aggregating them into very large multipliers is very challenging because of the large amount of soft logic required-especially in the form of long adders, and the high embedded multiplier count. In this paper, we describe a large multiplier architecture that operates in a multi-cycle format and which has a linear area/throughput ratio. We show results for a 2048-bit multiplier that has a latency of 118 cycles, inputs data every 9th cycle and closes timing at 377MHz in an Intel Arria 10 FPGA, and over 400MHz in a Stratix 10. the proposed multiplier uses 1/9 of the DSP resources typically used in a 2048-bit Karatsuba implementation, showing a perfectly linear throughput to DSP-count ratio. Our proposed solution outperforms recently reported results, in either arithmetic complexity-by making use of the Karatsuba techniques, or in scheduling efficiency-embedded DSP resources are fully utilized. © 2021 acm.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

An Optimal Implementation of an 8b/10b Encoder for Xilinx FPGAs 15

An Optimal Implementation of an 8b/10b Encoder for Xilinx FP...

引用

15th international symposium on Electronics and Telecommunications, ISETC 2022

作者： Popa, Stefan Coliban, Radu-Mihai Ivanovici, Mihai Transilvania University of Braşov Electronics and Computers Dept. Romania

ISBN: (纸本)9781665451505

We propose an optimal structural design of an 8b/10b encoder for Xilinx FPGAs. the proposed approach aims at reducing the number of look-up tables used for the implementation. We compare our design with two state-of-the-art solutions and two behavioral models. the implementation results show that our solution provides the lowest resource utilization, logic delay and power consumption. © 2022 IEEE.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Demystifying the memory system of modern datacenter fpgas for software programmers through microbenchmarking 21

Demystifying the memory system of modern datacenter fpgas fo...

引用

2021 acm/sigda international symposium on field-programmable gate arrays, FPGA 2021

作者： Lu, Alec Fang, Zhenman Liu, Weihua Shannon, Lesley Simon Fraser University Burnaby Canada

ISBN: (纸本)9781450382182

With the public availability of FPGAs from major cloud service providers like AWS, Alibaba, and Nimbix, hardware and software developers can now easily access FPGA platforms. However, it is nontrivial to develop efficient FPGA accelerators, especially for software programmers who use high-level synthesis (HLS). the major goal of this paper is to figure out how to efficiently access the memory system of modern datacenter FPGAs in HLS-based accelerator designs. this is especially important for memory-bound applications;for example, a naive accelerator design only utilizes less than 5% of the available off-chip memory bandwidth. To achieve our goal, we first identify a comprehensive set of factors that affect the memory bandwidth, including 1) the number of concurrent memory access ports, 2) the data width of each port, 3) the maximum burst access length for each port, and 4) the size of consecutive data accesses. then we carefully design a set of HLS-based microbenchmarks to quantitatively evaluate the performance of the Xilinx Alveo U200 and U280 FPGA memory systems when changing those affecting factors, and provide insights into efficient memory access in HLS-based accelerator designs. To demonstrate the usefulness of our insights, we also conduct two case studies to accelerate the widely used K-nearest neighbors (KNN) and sparse matrix-vector multiplication (SpMV) algorithms. Compared to the baseline designs, optimized designs leveraging our insights achieve about 3.5x and 8.5x speedups for the KNN and SpMV accelerators. © 2021 acm.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共30页 << < 1 2 3 4 5 6 7 8 9 10 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：