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Design of a ferroelectric programmable logic gate array

INTEGRATED FERROELECTRICS 2003年第1期56卷 1013-1021页

作者： Macleod, TC Ho, FD NASA George C Marshall Space Flight Ctr Huntsville AL 35812 USA Univ Alabama Dept Elect & Comp Engn Huntsville AL 35899 USA

A programmable logic gate array has been designed utilizing ferroelectric field effect transistors. the design has only a small number of gates, but this could be scaled up to a more useful size. Using FFETs in a logic array gives several advantages. First, it allows real-time programmability to the array to give high speed reconfiguration. It also allows the array to be configured nearly an unlimited number of times, unlike a FLASH FPGA. Finally, the Ferroelectric programmable Logic gate Array (FPLGA) can be implemented using a smaller number of transistors because of the inherent logic characteristics of an FFET. the devices were only designed and modeled using Spice models of the circuit, including the FFET. the actual device was not produced. the designs consist of a small array of logic gates. Other gates could easily be produced. they are linked by FFETs that control the logic flow. Timing and logic tables have been produced showing the array can produce a variety of logic combinations at a real time usable speed. this device could be a prototype for a device that could be put into imbedded systems that need the high speed of hardware implementation of logic and the complexity to need to change the logic algorithm. Because of the non-volatile nature of the FFET, it would also be useful in situations that needed to program a logic array once and use it repeatedly after the power has been shut off.

关键词： Formal logic programmable Logic arrays Logic gates Transistor Device Component High speed FFET arrays gates

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Analysis of the effect of LUT size on FPGA area and delay using theoretical derivations

Analysis of the effect of LUT size on FPGA area and delay us...

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6th international symposium on Quality Electronic Design

作者： Gao, HX Yang, YT Ma, XH Dong, G Xidian Univ Microelect Inst Xian 710071 Peoples R China

ISBN: (纸本)0769523013

Based on architecture analysis of island-style FPGA, area and delay models of LUT FPGA are proposed. the effect of LUT size on FPGA area and performance is studied. Results show optimal L UT size conclusion from computation models is same as that of experiments. A LUT size of 4 produces the best area results. A LUT size of 5 provides the better performance.

关键词： field programmable gate arrays (FPGA)

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Minimizing FPGA reconfiguration data at logic level 06

Minimizing FPGA reconfiguration data at logic level

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7th international symposium on Quality Electronic Design

作者： Raghuraman, Krishna Wang, Haibo Tragoudas, Spyros So Illinois Univ Carbondale IL 62901 USA

ISBN: (纸本)0769525237

A framework that relates the size of FPGA reconfiguration data to the number of minterms of a specially constructed function is presented. three techniques, variable mapping optimization, circuit don't-care modification, and look-up table input permutation, are developed to minimize minterms of the special function. the method to integrate the proposed techniques into FPGA design automation flow is discussed and experimental results are presented.

关键词： field programmable gate arrays Reconfigurable logic Table lookup Hardware Circuits Design automation Partitioning algorithms Routing Cost function Scheduling

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On routing demand and congestion estimation for FPGAs 7

On routing demand and congestion estimation for FPGAs

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7th Asia and South Pacific Design Automation Conference/15th international Conference on VLSI Design

作者： Balachandran, S Kannan, P Bhatia, D Univ Texas Erik Jonsson Sch Engn & Comp Sci Ctr Integrated Circuits & Syst Richardson TX 75083 USA

ISBN: (纸本)0769514413

Interconnection planning is becoming an important design issue for ASICs and large FPGAs. As the technology shrinks and the design density increases, proper planning of routing resources becomes all the more important to ensure rapid and feasible design convergence. One of the most important issues for planning interconnection is the ability to predict the routability of a given placed design. this paper provides insight into the workings of recently proposed method by Lou et. al. [8] and compares it with our proposed methodology, fGREP [6]. We have implemented the two methods for a generic FPGA architecture and compare the performance, accuracy and usability of their estimates. We use the well known FPGA physical design state VPR [2], as a common comparison tool. Our experiments show that fGREP produces far better routing estimates but at larger execution times than Lou's method. Insight into what makes the methods work and where they falter are also discussed in detail.

关键词： field programmable gate arrays (FPGA)

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Accelerating SSSP for Power-Law Graphs 22

Accelerating SSSP for Power-Law Graphs

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2022 acm/sigda international symposium on field-programmable gate arrays, FPGA 2022

作者： Chi, Yuze Guo, Licheng Cong, Jason University of California Los Angeles Los AngelesCA United States

ISBN: (纸本)9781450391498

the single-source shortest path (SSSP) problem is one of the most important and well-studied graph problems widely used in many application domains, such as road navigation, neural image reconstruction, and social network analysis. Although we have known various SSSP algorithms for decades, implementing one for large-scale power-law graphs efficiently is still highly challenging today, because - a work-efficient SSSP algorithm requires priority-order traversal of graph data, - the priority queue needs to be scalable both in throughput and capacity, and - priority-order traversal requires extensive random memory accesses on graph data. In this paper, we present SPLAG to accelerate SSSP for power-law graphs on FPGAs. SPLAG uses a coarse-grained priority queue (CGPQ) to enable high-throughput priority-order graph traversal with a large frontier. To mitigate the high-volume random accesses, SPLAG employs a customized vertex cache (CVC) to reduce off-chip memory access and improve the throughput to read and update vertex data. Experimental results on various synthetic and real-world datasets show up to a 4.9× speedup over state-of-the-art SSSP accelerators, a 2.6× speedup over 32-thread CPU running at 4.4 GHz, and a 0.9× speedup over an A100 GPU that has 4.1× power budget and 3.4× HBM bandwidth. Such a high performance would place SPLAG in the 14th position of the Graph 500 benchmark for data intensive applications (the highest using a single FPGA) with only a 45 W power budget. SPLAG is written in high-level synthesis C++ and is fully parameterized, which means it can be easily ported to various different FPGAs with different configurations. © 2022 acm.

关键词： field programmable gate arrays (FPGA)

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Evaluation of the streams-C C-to-FPGA compiler: An applications perspective 01

Evaluation of the streams-C C-to-FPGA compiler: An applicati...

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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)

作者： Frigo, J. Gokhale, M. Lavenier, D. Los Alamos National Laboratory Los Alamos NM 87545 United States

ISBN: (纸本)9781581133417

the Streams-C compiler ([5]) synthesizes hardware circuits for reconfigurable FPGA-based computers from parallel C programs. the Streams-C language consists of a small number of libraries and intrinsic functions added to a synthesizable subset of C, and supports a communicating process programming model. the processes may be either software or hardware processes, and the compiler manages communication among the processes transparently to the programmer. For the hardware processes, the compiler generates Register-Transfer-Level (RTL) VHDL, targeting multiple FPGAs with dedicated memories. For the software processes, a multi-threaded software program is generated. the Streams-C language and compiler offer a very high level of expressivity for reconfigurable computing application development, particularly for stream-processing applications. We find this is reflected in productivity, for a factor of up to 10 times improvement in time to produce a program. However, use of the tool in the "real world" is predicated on performance: only if such a compiler can deliver performance comparalble to hand-coded performance will it be used in practice. this paper presents an application study of the Streams-C compiler. Four applications have been written in Streams-C and compiled to the AMC Wildforce board containing Xilinx 4036's. those same applications have been hand-coded in a combination of RTL and structural VHDL. We compare performance of the generated code with the hand-optimized code. Our study shows that the compiler-generated designs are 1.37-4 times the area and 1/2-1 times the clock frequency of the hand designs. We find that the compiler, based on the SUIF infrastructure, can be greatly improved through various standard compiler optimizations that are not currently being exploited. thus we are currently rewriting a public domain version of Streams-C to better optimize and target the Virtex chip.

关键词： field programmable gate arrays

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Haptic Rendering of Deformable Objects Using a Multiple FPGA Parallel Computing Architecture 10

Haptic Rendering of Deformable Objects Using a Multiple FPGA...

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18th acm international symposium on field-programmable gate arrays

作者： Mandavikhah, Behzad Mafi, Ramin Sirouspour, Shahin Nicolici, Nicola McMaster Univ Hamilton ON Canada

ISBN: (纸本)9781605589114

High-fidelity simulations of haptic interaction with deformable objects is computationally challenging. In this paper, hardware-based parallel computing is proposed for finite-element (FE) analysis of soft-object deformation models. A distributed implementation of the Preconditioned Conjugate Gradient (PCG) algorithms on N field programmable gate Array (FPGA) devices can solve the large system of equations arising from FE models at high update rates required for stable haptic interaction. Massive parallelization of the computations is achieved by customizing the hardware architecture to the problem at hand and concurrently employing a large number of adaptive fixed-point computing units. An implementation of this scalable hardware accelerator on four Altera EP3SE110 FPGA devices is capable of performing 230.4 Giga Operations per second in Sparse Matrix by Vector (SpMxV) multiplication. this architecture has successfully enabled real-time simulation of haptic interaction with a 3-dimensional FE model of 6000 nodes at an update rate of 200 Hz. Both static and dynamic linear elastic models have been successfully simulated.

关键词： field-programmable gate array (FPGA) Finite-element method (FEM) Conjugate Gradient (CG) Soft-object deformation

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Demystifying the memory system of modern datacenter fpgas for software programmers through microbenchmarking 21

Demystifying the memory system of modern datacenter fpgas fo...

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2021 acm/sigda international symposium on field-programmable gate arrays, FPGA 2021

作者： Lu, Alec Fang, Zhenman Liu, Weihua Shannon, Lesley Simon Fraser University Burnaby Canada

ISBN: (纸本)9781450382182

With the public availability of FPGAs from major cloud service providers like AWS, Alibaba, and Nimbix, hardware and software developers can now easily access FPGA platforms. However, it is nontrivial to develop efficient FPGA accelerators, especially for software programmers who use high-level synthesis (HLS). the major goal of this paper is to figure out how to efficiently access the memory system of modern datacenter FPGAs in HLS-based accelerator designs. this is especially important for memory-bound applications;for example, a naive accelerator design only utilizes less than 5% of the available off-chip memory bandwidth. To achieve our goal, we first identify a comprehensive set of factors that affect the memory bandwidth, including 1) the number of concurrent memory access ports, 2) the data width of each port, 3) the maximum burst access length for each port, and 4) the size of consecutive data accesses. then we carefully design a set of HLS-based microbenchmarks to quantitatively evaluate the performance of the Xilinx Alveo U200 and U280 FPGA memory systems when changing those affecting factors, and provide insights into efficient memory access in HLS-based accelerator designs. To demonstrate the usefulness of our insights, we also conduct two case studies to accelerate the widely used K-nearest neighbors (KNN) and sparse matrix-vector multiplication (SpMV) algorithms. Compared to the baseline designs, optimized designs leveraging our insights achieve about 3.5x and 8.5x speedups for the KNN and SpMV accelerators. © 2021 acm.

关键词： field programmable gate arrays (FPGA)

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Artificial neural network implementation on a single FPGA of a pipelined on-line backpropagation 13

Artificial neural network implementation on a single FPGA of...

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13th international symposium on System Synthesis (ISSS 2000)

作者： Gadea, R Cerdá, J Ballester, F Mocholí, A Univ Politecn Valencia Dept Elect Engn Valencia 46022 Spain

ISBN: (纸本)0769507662

the paper describes the implementation of a systolic array for a multilayer perceptron on a Virtex XCV400 FPGA with a hardware-friendly learning algorithm. A pipelined adaptation of the on-line backpropagation algorithm is shown. Parallelism is better exploited because both forward and backward phases can be performed simultaneously. We can implement very large interconnection layers by using large Xilinx devices with embedded memories alongside the projection used in the systolic architecture. these physical and architectural features - together with the combination of FPGA reconfiguration properties with a design flow based on generic VHDL - create an easy, flexible, and fast method of designing a complete ANN on a single FPGA. the result offers a high degree of parallelism and fast performance.

关键词： Arithmetic Artificial neural networks Backpropagation algorithms field programmable gate arrays Logic arrays Logic devices Neural networks Neurons Signal processing algorithms Systolic arrays

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FPGA-based Low-Cost Real-Time Face Recognition 15

FPGA-based Low-Cost Real-Time Face Recognition

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15th IEEE international symposium on Intelligent Systems and Informatics (SISY)

作者： Schaffer, Laszlo Kincses, Zoltan Pletl, Szilveszter Univ Szeged Dept Tech Informat H-6725 Szeged Hungary Subotica Tech Collage Appl Sci Subotica Serbia

ISBN: (纸本)9781538638552

Nowadays face recognition plays a central role in surveillance, biometrics and security. In this paper a field programmable gate Array (FPGA) based low-cost real-time architecture for face recognition is presented. the face recognition module receives the detected faces from a video stream and processes the data with the widely used Eigenfaces, also known as the Principal Component Analysis (PCA) algorithm. the architecture is implemented on a low-cost Zynq-Z7010 FPGA. the proposed architecture is a part of a system, that capable of finding faces in a crowd based on a preliminarily defined set of faces. In the future it can be integrated into real-time surveillance systems of frequently crowded places (e.g. airports, bus stations), to sort out the supposed sources of threat, and hereby reduce the risk of possible criminal actions.

关键词： Face Face recognition field programmable gate arrays Principal component analysis Real-time systems Computer architecture Training

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